Application of hot-carrier reliability simulation to memory and ASIC design

Abstract

We have applied hot-carrier circuit-level reliability simulation to memory and ASIC logic products. We used two different approaches: for memory products we applied circuit-level simulation to entire circuits to over 12k transistors, so that areas with the worst degradation are not missed due to simulating only certain circuit blocks. We present applications to DRAM and SRAM products, and a design curve to directly relate device-level degradation to circuit degradation. For 0.18 /spl mu/m and 0.14 /spl mu/m logic products, we analyzed simple inverters to create design guidelines for maximum transition time to screen delay library cells to ensure adequate reliability. At 200 MHz, maximum transition time (0-100%) was 0.8 ns (17% or duty) for speed degradation of 5% after a 10-year operating lifetime. Analyzing an 800,000 net product required only a couple of hours. We screened out 30 nets, which were later judged reliable due to their reduced signal duty.