Fully-depleted SOI NMOS transistors with p/sup +/-polysilicon gate

Sun Hai-feng, Liu Xin-yu, Hai Chao-he, Wu De-xin
{"title":"Fully-depleted SOI NMOS transistors with p/sup +/-polysilicon gate","authors":"Sun Hai-feng, Liu Xin-yu, Hai Chao-he, Wu De-xin","doi":"10.1109/ICSICT.2001.981595","DOIUrl":null,"url":null,"abstract":"p/sup +/ polysilicon and n/sup +/ polysilicon were used as the gate material for fully-depleted SOI NMOS transistors. It's found that n-channel transistors with p+ poly gates require lower channel doping levels than their n/sup +/ poly counterparts, leading to easier formation of depleted film and control of the threshold voltage. The low channel doping results in improved source-drain breakdown characteristic.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2001.981595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

p/sup +/ polysilicon and n/sup +/ polysilicon were used as the gate material for fully-depleted SOI NMOS transistors. It's found that n-channel transistors with p+ poly gates require lower channel doping levels than their n/sup +/ poly counterparts, leading to easier formation of depleted film and control of the threshold voltage. The low channel doping results in improved source-drain breakdown characteristic.
具有p/sup +/-多晶硅栅极的全耗尽SOI NMOS晶体管
采用p/sup +/多晶硅和n/sup +/多晶硅作为全耗尽SOI NMOS晶体管的栅极材料。研究发现,具有p+多晶硅栅极的n沟道晶体管比其n/sup +/多晶硅栅极晶体管需要更低的沟道掺杂水平,从而更容易形成耗尽膜和控制阈值电压。低通道掺杂改善了源漏击穿特性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信