Gate width optimization of PHEMT MMIC LNA for low power consumption

Abstract

We have developed C-band LNAs of a very low noise and of a very low power dissipation by using a commercially standard 0.25 /spl mu/m T gate PHEMT technology. A 2-stage MMIC LNA of very low noise figure as low as 0.76 dB and gain of 16 dB at 5.4 GHz has been implemented using a minimum input matching network. Also an LNA of very low power consumption as small as 18 mW with 3 V power supply has been implemented using an optimization of gate width and circuit topology.