发布求助
文献互助 智能选刊 最新文献

1997 IEEE International SOI Conference Proceedings最新文献

筛选
英文 中文
A general physical model for short-channel double-gate SOI MOSFETS 短沟道双栅SOI mosfet的一般物理模型
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634945
Zheming Li, J. Woo
{"title":"A general physical model for short-channel double-gate SOI MOSFETS","authors":"Zheming Li, J. Woo","doi":"10.1109/SOI.1997.634945","DOIUrl":"https://doi.org/10.1109/SOI.1997.634945","url":null,"abstract":"Previous works on the modeling of short-channel double-gate devices in the above-threshold regime were based mainly on modifying the current expressions for bulk devices. These models would probably be of limited utility because they do not account for the central physical characteristic of the double-gate devices, namely the coupling of the two channels. In this paper, we present a general physical model which explicitly accounts for physical effects such as channel coupling and drain induced conductance enhancement (DICE). The model is a major extension of the single-gate SOI MOSFET model to the double-gate case.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134315878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A comparative study of SOI inverter circuits for low-voltage and low-power applications 低电压和低功耗SOI逆变电路的比较研究
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634958
W. Jin, C. Chan
{"title":"A comparative study of SOI inverter circuits for low-voltage and low-power applications","authors":"W. Jin, C. Chan","doi":"10.1109/SOI.1997.634958","DOIUrl":"https://doi.org/10.1109/SOI.1997.634958","url":null,"abstract":"Substantial progress has been made in SOI technology for low-voltage and low-power applications in recent years. Novel SOI devices, with the capabilities of low power and high performance, have been proposed, modeled and fabricated. A comparison of these devices at circuit level is highly required. However, previous works are either incomplete or at device level. In this paper, a comparative study of inverter circuits composed of four types of SOI devices is conducted based on MEDICI simulation.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134133874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improving ITOX conditions for low defect density and BOX breakdown 改善ITOX条件，实现低缺陷密度和BOX击穿
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634909
J. Schwank, M. Anc, M. Shaneyfelt, B. Draper, T.L. Meisenheimer, W. L. Warren, K. Vanheusden, D. Fleetwood, L.P. Schanwald
{"title":"Improving ITOX conditions for low defect density and BOX breakdown","authors":"J. Schwank, M. Anc, M. Shaneyfelt, B. Draper, T.L. Meisenheimer, W. L. Warren, K. Vanheusden, D. Fleetwood, L.P. Schanwald","doi":"10.1109/SOI.1997.634909","DOIUrl":"https://doi.org/10.1109/SOI.1997.634909","url":null,"abstract":"A narrow dose-energy process window exists for the formation of high-quality low dose SIMOX layers. Process instabilities require annealing schemes that enlarge the process window to improve manufacturability. As recently shown, the integrity of thin buried oxides has been improved by annealing in a highly oxidizing ambient. In this work, we extend the investigations to the effects of high temperature oxidation on the integrity and radiation hardness of the thin BOX SIMOX implanted with doses from the extreme ends of the process window. In addition, we explore the effects of moderate temperature H/sub 2/ anneals on BOX integrity.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131082463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design criteria for a fully depleted-0.1 /spl mu/m SOI technology 完全耗尽的设计标准-0.1 /spl mu/m SOI技术
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634941
J. Burns, R. Frankel, A. Soares, P. Wyatt
{"title":"Design criteria for a fully depleted-0.1 /spl mu/m SOI technology","authors":"J. Burns, R. Frankel, A. Soares, P. Wyatt","doi":"10.1109/SOI.1997.634941","DOIUrl":"https://doi.org/10.1109/SOI.1997.634941","url":null,"abstract":"A sub-0.25 /spl mu/m fully depleted silicon-on-insulator (FDSOI) technology has been developed and fully scaled ring oscillators fabricated using 193-nm lithography. This technology is being extended by incorporating phase shift techniques with 193-nm lithography to fabricate polysilicon gates with 0.1 /spl mu/m drawn channel lengths. The purpose of this paper is to define the process and design requirements for a fully depleted, 0.1 /spl mu/m SOI technology and predict the performance characteristics of 0.1 /spl mu/m ring oscillators.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133981382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Metastability of SOI CMOS latches SOI CMOS锁存器的亚稳态
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634983
C. Tretz, C. Chuang, L. Terman, C. Anderson, C. Zukowski
{"title":"Metastability of SOI CMOS latches","authors":"C. Tretz, C. Chuang, L. Terman, C. Anderson, C. Zukowski","doi":"10.1109/SOI.1997.634983","DOIUrl":"https://doi.org/10.1109/SOI.1997.634983","url":null,"abstract":"SOI has recently emerged as a serious contender for low-power high-performance applications. This paper examines the metastability of CMOS latches based on partially-depleted (PD) SOI devices with various body-connection topologies.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Novel polysilicon sidewall gate silicon-on-sapphire MOSFET for power amplifier applications 用于功率放大器的新型多晶硅侧壁栅极蓝宝石上硅MOSFET
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634970
R.A. Johnson, S. Kasa, P. de la Houssaye, G. Garcia, I. Lagnado, P. Asbeck
{"title":"Novel polysilicon sidewall gate silicon-on-sapphire MOSFET for power amplifier applications","authors":"R.A. Johnson, S. Kasa, P. de la Houssaye, G. Garcia, I. Lagnado, P. Asbeck","doi":"10.1109/SOI.1997.634970","DOIUrl":"https://doi.org/10.1109/SOI.1997.634970","url":null,"abstract":"We report the processing and DC and microwave characteristics of a novel thin-film silicon-on-sapphire MOS transistor which utilizes a sidewall process to realize a deep sub-micron gate length without the use of lithography. The device also incorporates an asymmetric lightly doped drain region for high breakdown voltage. Devices with 0.15 and 0.25 /spl mu/m gate lengths have been fabricated. A FET with a 0.25 /spl mu/m gate length and 1.0 /spl mu/m LDD length had an f/sub t/=9 GHz, f/sub max/=27 GHz and breakdown voltage of 13 volts.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122319109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.35 /spl mu/m 560 KG SOI/CMOS gate array using field-shield isolation technique 采用场屏蔽隔离技术的0.35 /spl mu/m 560kg SOI/CMOS门阵列
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634985
K. Mashiko, K. Ueda, K. Nii, Y. Wada, T. Hirota, S. Maeda, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, S. Maegawa, H. Hamano
{"title":"A 0.35 /spl mu/m 560 KG SOI/CMOS gate array using field-shield isolation technique","authors":"K. Mashiko, K. Ueda, K. Nii, Y. Wada, T. Hirota, S. Maeda, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, S. Maegawa, H. Hamano","doi":"10.1109/SOI.1997.634985","DOIUrl":"https://doi.org/10.1109/SOI.1997.634985","url":null,"abstract":"Summary form only given. SOI/CMOS devices have been developed not only for memory LSIs but also for logic LSIs. Some of the recent works include gate arrays having 220-320 K usable gates and operating at a 2.0 V supply voltage. As the history of bulk/CMOS devices indicate, the market will demand SOI/CMOS gate array to integrate more and more gates and operate at lower and lower supply voltages to reduce power consumption. This paper describes a 1.0 V 560 KG SOI/CMOS gate array using 0.35 /spl mu/m partially-depleted transistors to meet this demand. The field-shield isolation technique stabilizes the body potential of transistors sufficiently to suppress the floating-body problems. Also the technique eliminates the leakage current flowing through the transistor edge to suppress the standby current under sub-threshold leakage-level.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123588457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low dose SIMOX and impact of ITOX process on quality of SOI film 低剂量SIMOX及其ITOX工艺对SOI膜质量的影响
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634911
W. Maszara, J. Bennett, T. Boden, R. Dockerty, C. Gondran, S. Jackett-Murphy, P. Vasudev, M. Anc, H. Hovel
{"title":"Low dose SIMOX and impact of ITOX process on quality of SOI film","authors":"W. Maszara, J. Bennett, T. Boden, R. Dockerty, C. Gondran, S. Jackett-Murphy, P. Vasudev, M. Anc, H. Hovel","doi":"10.1109/SOI.1997.634911","DOIUrl":"https://doi.org/10.1109/SOI.1997.634911","url":null,"abstract":"Summary form only given. Internal thermal oxidation (ITOX) has been shown to improve the quality of buried oxide (BOX) in low dose (4E17 cm/sup -2/) SOI SIMOX material. SOI film quality of ITOX SIMOX was determined to be as good as bulk in terms of the integrity of gate oxide grown on it. We have investigated low dose SIMOX material and the impact of its high temperature annealing as well as the subsequent ITOX process on structure and electrical properties of its SOI film. Several new findings about the SOI film quality and its relationship to process parameters are reported.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130183025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SIMOX voltage references for applications up to 275/spl deg/C using the threshold voltage difference principle 使用阈值电压差原理，适用于高达275/spl度/C的SIMOX电压参考
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634957
C. Eisenhut, J. W. Klein
{"title":"SIMOX voltage references for applications up to 275/spl deg/C using the threshold voltage difference principle","authors":"C. Eisenhut, J. W. Klein","doi":"10.1109/SOI.1997.634957","DOIUrl":"https://doi.org/10.1109/SOI.1997.634957","url":null,"abstract":"This paper will present SIMOX voltage reference circuits using the threshold voltage difference principle for applications up to 275/spl deg/C. We have performed measurements concerning temperature-, supply voltage-, load current- and long term-stability.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125886382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Local floating body effect in body-grounded SOI nMOSFETs 体接地SOI nmosfet中的局部浮体效应
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634915
Y. Tseng, W.M. Huang, B. Ikegami, D. Diaz, J. Ford, J. Woo
{"title":"Local floating body effect in body-grounded SOI nMOSFETs","authors":"Y. Tseng, W.M. Huang, B. Ikegami, D. Diaz, J. Ford, J. Woo","doi":"10.1109/SOI.1997.634915","DOIUrl":"https://doi.org/10.1109/SOI.1997.634915","url":null,"abstract":"Summary form only given. In this paper, the width dependence of the kink effect and the low frequency noise overshoot in the body grounded H-gate SOI MOSFETs have been studied. These phenomena are related to the local floating body effects resulting from the intrinsic body impedance. Also, it is suggested that the unique low frequency noise overshoot in SOI can be a sensitive tool to evaluate the efficiency of the body contact.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121901820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信