R.A. Johnson, S. Kasa, P. de la Houssaye, G. Garcia, I. Lagnado, P. Asbeck
{"title":"用于功率放大器的新型多晶硅侧壁栅极蓝宝石上硅MOSFET","authors":"R.A. Johnson, S. Kasa, P. de la Houssaye, G. Garcia, I. Lagnado, P. Asbeck","doi":"10.1109/SOI.1997.634970","DOIUrl":null,"url":null,"abstract":"We report the processing and DC and microwave characteristics of a novel thin-film silicon-on-sapphire MOS transistor which utilizes a sidewall process to realize a deep sub-micron gate length without the use of lithography. The device also incorporates an asymmetric lightly doped drain region for high breakdown voltage. Devices with 0.15 and 0.25 /spl mu/m gate lengths have been fabricated. A FET with a 0.25 /spl mu/m gate length and 1.0 /spl mu/m LDD length had an f/sub t/=9 GHz, f/sub max/=27 GHz and breakdown voltage of 13 volts.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Novel polysilicon sidewall gate silicon-on-sapphire MOSFET for power amplifier applications\",\"authors\":\"R.A. Johnson, S. Kasa, P. de la Houssaye, G. Garcia, I. Lagnado, P. Asbeck\",\"doi\":\"10.1109/SOI.1997.634970\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report the processing and DC and microwave characteristics of a novel thin-film silicon-on-sapphire MOS transistor which utilizes a sidewall process to realize a deep sub-micron gate length without the use of lithography. The device also incorporates an asymmetric lightly doped drain region for high breakdown voltage. Devices with 0.15 and 0.25 /spl mu/m gate lengths have been fabricated. A FET with a 0.25 /spl mu/m gate length and 1.0 /spl mu/m LDD length had an f/sub t/=9 GHz, f/sub max/=27 GHz and breakdown voltage of 13 volts.\",\"PeriodicalId\":344728,\"journal\":{\"name\":\"1997 IEEE International SOI Conference Proceedings\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.1997.634970\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1997.634970","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel polysilicon sidewall gate silicon-on-sapphire MOSFET for power amplifier applications
We report the processing and DC and microwave characteristics of a novel thin-film silicon-on-sapphire MOS transistor which utilizes a sidewall process to realize a deep sub-micron gate length without the use of lithography. The device also incorporates an asymmetric lightly doped drain region for high breakdown voltage. Devices with 0.15 and 0.25 /spl mu/m gate lengths have been fabricated. A FET with a 0.25 /spl mu/m gate length and 1.0 /spl mu/m LDD length had an f/sub t/=9 GHz, f/sub max/=27 GHz and breakdown voltage of 13 volts.