{"title":"Semiconductor layer transfer by anodic wafer bonding","authors":"T. Lee, Q. Tong, Y. Chao, L. Huang, U. Gosele","doi":"10.1109/SOI.1997.634922","DOIUrl":"https://doi.org/10.1109/SOI.1997.634922","url":null,"abstract":"High quality and low cost single crystalline semiconductor on glass (SOG) wafers are highly desirable, e.g., for flat panel displays and solar cells (Si on glass), sensors (Ge on glass) and GaN growth (SiC on glass). SOG wafers can be realized by hydrogen implanted Si wafer bonding and layer splitting (\"Smart Cut\") which saves the Si substrate and is an environmentally friendly technique. However, almost no information on the process design has been revealed. In this work we discuss the design guidelines for SOG preparation using anodic bonding and the layer splitting approach.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116984071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Screening SOI substrates for radiation resistant space electronics applications","authors":"S.T. Liu, J. Yue, J. Schrankler","doi":"10.1109/SOI.1997.634906","DOIUrl":"https://doi.org/10.1109/SOI.1997.634906","url":null,"abstract":"Total device isolation, speed, density, and radiation hardness (SEU) are significant advantages of silicon-on-insulator (SOI) substrates over bulk Si substrates. Taking advantage of these properties, we have been manufacturing partially depleted SOI/CMOS VLSI SRAMs (256K and 1M) and high density digital ASIC (>400K usable gates) chips for space electronics application in radiation harsh environments using full dose SIMOX (1.7-1.8/spl times/10/sup 18/ cm/sup -2/ dose at 190-200 keV) materials for some time. The full dose SIMOX wafers have been supplied with and without oxide caps from the manufacturers. The thickness of the top silicon and the thickness of the buried oxide after annealing are approximately 200-230 nm and 380 nm respectively. During the preparation of SIMOX wafers for production, practically all yield limiting issues of SIMOX technology were addressed: particles, HF defects, pipes (BOX pinholes), roughness, dislocations, thickness uniformity of top silicon and buried oxide, buried oxide pipes, Si islands in the buried oxide and unintentional background doping contamination on top silicon of the SOI materials. Poor functional yield has been correlated with particles on incoming materials. A nondestructive particle screening method was proposed and a database has been kept for every incoming SIMOX wafer. In addition, high standby currents were found to be associated with various defects (metallic contamination, dislocations, HF defects, buried oxide pipes, etc.) and unintentional impurity contamination.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123248117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and analysis of a novel mixed accumulation/inversion mode FD SOI MOSFET","authors":"F.L. Daun, D. Ioannou","doi":"10.1109/SOI.1997.634952","DOIUrl":"https://doi.org/10.1109/SOI.1997.634952","url":null,"abstract":"In this paper, a new fully-depleted SOI MOSFET device is designed and analyzed, which combines the advantages of both the inversion mode and the accumulation mode devices: its performance is better than the inversion mode device, and its breakdown voltage higher than the accumulation mode device. Additionally, the new device results in better hot carrier reliability.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"436 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115578898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Edholm, L. Vestling, M. Bergh, S. Tiensuu, A. Soderbarg
{"title":"Silicon-on-diamond MOS-transistors with thermally grown gate oxide","authors":"B. Edholm, L. Vestling, M. Bergh, S. Tiensuu, A. Soderbarg","doi":"10.1109/SOI.1997.634917","DOIUrl":"https://doi.org/10.1109/SOI.1997.634917","url":null,"abstract":"Summary form only given. Self-heating in Silicon-On-Insulator (SOI) devices has during the past years attracted lots of attention and is a problem that remains to be solved. It has, furthermore, been shown that in smart power devices, thick buried oxides of 3 /spl mu/m or more are desired to prevent the substrate potential to lower breakdown voltages. However, these thicker buried oxides will only aggravate the thermal limitations imposed by the buried oxide. Due to the outstanding thermal properties of diamond compared to silicon dioxide, it would consequently be advantageous if silicon dioxide could be replaced with diamond in future SOI materials. Even though it has been shown that diamond is compatible with conventional silicon processing, no MOS-transistors with thermally grown gate oxide has been manufactured up to date, due to the difficulty in protecting diamond during furnace oxidations. In this paper Silicon-On-Diamond (S-O-D) MOS-transistors with thermally grown gate oxide are presented for the first time.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116099446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Agarwal, T. E. Haynes, V. Venezia, D. Eaglesham, M.K. Welson, Y. Chabal, O. W. Holland
{"title":"Efficient production of silicon-on-insulator films by co-implantation of He/sup +/ with H/sup +/","authors":"A. Agarwal, T. E. Haynes, V. Venezia, D. Eaglesham, M.K. Welson, Y. Chabal, O. W. Holland","doi":"10.1109/SOI.1997.634924","DOIUrl":"https://doi.org/10.1109/SOI.1997.634924","url":null,"abstract":"The thin film separation process with H/sup +/ proceeds by both chemical interactions (bond breaking and internal surface passivation) and physical interaction (gas coalescence, pressure, fracture) of implanted H/sup +/ with the Si substrate. It is difficult to isolate the contribution of each component to the overall process using implantation of H only. In this work, we have combined H/sup +/ and He/sup +/ gas implantation to decouple the physical and chemical contributions to the blistering and thin film separation processes. We have observed that combination of H and He gas implants results in a synergistic effect that allows the threshold dose for both processes to be significantly reduced.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114423293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fabrication of Si/SiO/sub 2/ Bragg reflectors by low energy multiple SIMOX","authors":"Y. Ishikawa, N. Shibata, S. Fukatsu","doi":"10.1109/SOI.1997.634931","DOIUrl":"https://doi.org/10.1109/SOI.1997.634931","url":null,"abstract":"We report successful fabrication of SIMOX-based epitaxial Bragg reflectors (BRs) to demonstrate the yet-to-be-explored potential of current SIMOX technology for conceivable optical applications.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SOI MOSFET mismatch due to floating-body effects","authors":"J. Mandelman, F. Assaderaghi, L. Hsu","doi":"10.1109/SOI.1997.634984","DOIUrl":"https://doi.org/10.1109/SOI.1997.634984","url":null,"abstract":"To distinguish small differentials in voltage, circuits such as sense amplifiers and SRAM cells require transistors having closely matched electrical characteristics. For example, a mismatch in threshold voltage between cross-coupled NMOSFETs in a sense amplifier introduces an additional noise source which hinders reliable sensing. Mismatch in V/sub T/ results from mismatched body-charge state, which is dependent on the operating history of the MOSFETs. In this paper, the effect of transient operation of cross-coupled partially-depleted SOI NMOSFETs on the mismatch of device electrical characteristics is investigated with FIELDAY device modeling. Selective use of novel \"body-equilibration links\" allows closely matched electrical characteristics within groups of devices without seriously degrading the performance advantages of SOI.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128416708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Kink-free analog circuit design with floating-body NFD/SOI CMOS: a current-steering D-A converter","authors":"D. Chang, J. Fossum, S. Reynolds, M. Pelella","doi":"10.1109/SOI.1997.634981","DOIUrl":"https://doi.org/10.1109/SOI.1997.634981","url":null,"abstract":"Summary form only given. MOSFETs built on SOI have yielded superior performance in RF (>1 GHz) applications mainly because of the inherent device isolation afforded by the underlying oxide. However, the floating-body (FB) non-fully depleted (NFD) SOI MOSFET has not been seriously considered as an option for analog circuits since it suffers from the kink effect. In this paper, we present a novel approach to ensure kink-free operation of FB-NFD/SOI analog circuits, using it in the design of a 10-bit current-steering D-A Converter (DAC). SOISPICE-4.4, with its device models upgraded and refined for high-frequency analog applications, is used to simulate the DAC and verify the design approach.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs","authors":"Liqiong Wei, Zhanping Chen, K. Roy","doi":"10.1109/SOI.1997.634943","DOIUrl":"https://doi.org/10.1109/SOI.1997.634943","url":null,"abstract":"In this paper, double gate dynamic threshold voltage (DGDT) SOI MOSFETs, which combine the advantages of DTMOS and FD SOI MOSFETs without the limitation of the supply voltage, are simulated using SOI-SPICE4.4. The threshold voltages, leakage currents and drive currents for FD SOI MOSFETs and DGDT SOI MOSFETs are compared. DGDT SOI MOSFETs show symmetric characteristics and the best I/sub on/I(off)/. Excellent DC inverter characteristics down to 0.15 V and good full adder performance at 1V are shown. The propagation delay and the average power consumption of the full adder are 0.625 ns and 11.5 /spl mu/W, respectively. It can be seen that DGDT SOI MOSFET is a good candidate for low power high performance designs.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121540688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Nakamura, K. Imai, H. Onishi, K. Kumagai, T. Yamada, K. Iwaki, Y. Matsubara, T. Ishigami, S. Furosawa, T. Horiuchi
{"title":"High performance dual-gate FD-SOI CMOS process with an ultra thin TiSi/sub 2/","authors":"I. Nakamura, K. Imai, H. Onishi, K. Kumagai, T. Yamada, K. Iwaki, Y. Matsubara, T. Ishigami, S. Furosawa, T. Horiuchi","doi":"10.1109/SOI.1997.634914","DOIUrl":"https://doi.org/10.1109/SOI.1997.634914","url":null,"abstract":"Summary form only given. We have developed a manufacturable FD-SOI 0.35 /spl mu/m CMOS process with an ultra thin TiSi/sub 2/ film. We obtained sheet resistance of 10 /spl Omega//sq. for N/sup +/ and P/sup +/ SOI diffusions, and saturation current of 1.8 mA and 0.56 mA for NMOS and PMOS transistors (V/sub D/=V/sub G/=1.5 V, W=10 /spl mu/m), respectively. The feasibility of the process has been verified successfully by fabricating a 128 kbit SRAM.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129406723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}