1997 IEEE International SOI Conference Proceedings最新文献

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Behavior of indium in thin SOI films 铟在SOI薄膜中的行为
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634936
J. Jacobs, R. Schiebel, K. Joyner, T. Houston
{"title":"Behavior of indium in thin SOI films","authors":"J. Jacobs, R. Schiebel, K. Joyner, T. Houston","doi":"10.1109/SOI.1997.634936","DOIUrl":"https://doi.org/10.1109/SOI.1997.634936","url":null,"abstract":"The behavior of indium implanted in silicon-on-insulator (SOI) material is explored by using SIMS analysis to obtain the doping concentration profile as a function of the silicon film thickness for a fixed implant depth, and as a function of the implant depth for a fixed silicon film thickness. Based on the experimental data, the following observations can be made. Indium can be highly mobile and can diffuse throughout the buried oxide. As a result, there is a dopant depletion zone near the buried oxide interface. The indium doping profile can be practically invariant under certain implant conditions in thicker films. As a result of indium's highly mobile nature, a lower temperature process is necessary to maintain the as-implanted indium profile in thin-film SOI transistors.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131164519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic effects in BTG/SOI MOSFETs and circuits due to distributed body resistance 分布体电阻对BTG/SOI mosfet和电路的动态影响
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634916
G. Workman, J. Fossum
{"title":"Dynamic effects in BTG/SOI MOSFETs and circuits due to distributed body resistance","authors":"G. Workman, J. Fossum","doi":"10.1109/SOI.1997.634916","DOIUrl":"https://doi.org/10.1109/SOI.1997.634916","url":null,"abstract":"Summary form only given. The SOI MOSFET with body tied to gate (BTG) has been proposed for low-voltage CMOS applications. Clearly for DC or quasi-static conditions, the BTG device will have reduced threshold voltage (V/sub T/) when on due to the body bias, and hence increased drive current. Thus BTG/SOI CMOS can conceivably be designed with nominal V/sub T/ high enough to avoid excessive static power while giving good speed performance. Thin-film SOI is the preferred technology for BTG MOSFETs because of minimal source/drain junction area and hence less recombination current in the gate. However, the effects of inherent body resistance in the BTG tie, which have not been addressed in depth, are an issue. In this paper, we present insightful results of circuit simulations that reveal dynamic effects of the finite and distributed body resistance and that give insight concerning optimal design of BTG/SOI CMOS devices and circuits.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116372439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A model for SIMOX buried-oxide low-field conduction and trapping SIMOX埋地氧化物低场传导和捕集模型
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634927
J. Krska, J. Yoon, J. E. Chung
{"title":"A model for SIMOX buried-oxide low-field conduction and trapping","authors":"J. Krska, J. Yoon, J. E. Chung","doi":"10.1109/SOI.1997.634927","DOIUrl":"https://doi.org/10.1109/SOI.1997.634927","url":null,"abstract":"Intrinsic SIMOX buried oxide (BOX) low-field conduction and trapping, which is not due to defect-related \"piping\", has been previously observed for E-fields <3 MV/cm/sup 2/. However, fundamental understanding of this phenomenon is still lacking. This study presents a new SIMOX BOX low-field conduction and trapping model, which takes into account the specific role of the BOX microstructure, i.e. BOX silicon-richness and the presence of BOX silicon islands. This model explains the observed SIMOX BOX conduction and charge-trapping characteristics as well as the correlation between low-field and high-field BOX conduction.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129326306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The HgFET: a new characterization tool for SOI silicon film properties HgFET:一种新的SOI硅膜性能表征工具
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634992
H. Hovel
{"title":"The HgFET: a new characterization tool for SOI silicon film properties","authors":"H. Hovel","doi":"10.1109/SOI.1997.634992","DOIUrl":"https://doi.org/10.1109/SOI.1997.634992","url":null,"abstract":"Summary form only given. SOI starting wafer characterization relies heavily on non-destructive measurements such as thickness, uniformity, and lifetime. Leakage current through the BOX is sometimes measured and used to determine an electrical defect density. The electrical quality of the Si film is less well known. One device that can be used to assess Si film properties is the \"pseudo-FET\" in which point contacts made to the film act as the source and drain while the substrate and BOX act as the gate electrode and oxide. However, the point contacts act as Schottky barriers and the characteristics are pressure sensitive, somewhat limiting the properties that can be measured. A new version of the pseudo-FET called the HgFET is described here, in which a combination of broad area Hg electrodes coupled with special surface treatment are used to overcome the limitations of point contacts. The HgFET can be used for quality control of the starting Si film, yielding the electron and hole mobilities, the BOX charge, the interface state density, the doping level, the hole and electron transconductances, the flatband voltage, the linear and saturated threshold voltages, and the mobility versus field.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126343363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
High-sensitivity measurement of particles on SOI wafers SOI晶圆上颗粒的高灵敏度测量
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634993
H. Naruoka, Y. Yoshida, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Yamamoto
{"title":"High-sensitivity measurement of particles on SOI wafers","authors":"H. Naruoka, Y. Yoshida, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Yamamoto","doi":"10.1109/SOI.1997.634993","DOIUrl":"https://doi.org/10.1109/SOI.1997.634993","url":null,"abstract":"In this report, it is found that particles on SOI wafers can be measured with high-sensitivity by inspection equipment with cell-to-cell image comparison. COPs were directly and non-destructively observed on SOI wafers for the first time by means of this measurement.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122587457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Carrier recombination lifetime measurement of bonded SOI wafers by microwave photoconductivity decay method 微波光导衰减法测定键合SOI晶圆载流子复合寿命
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634962
S. Ahmed, B. Catarini, S. Lizotte, K. Iba, H. Hashizume, S. Sumie
{"title":"Carrier recombination lifetime measurement of bonded SOI wafers by microwave photoconductivity decay method","authors":"S. Ahmed, B. Catarini, S. Lizotte, K. Iba, H. Hashizume, S. Sumie","doi":"10.1109/SOI.1997.634962","DOIUrl":"https://doi.org/10.1109/SOI.1997.634962","url":null,"abstract":"Microwave photoconductivity decay (/spl mu/PCD) method was used for the measurement of bulk carrier recombination lifetime of bonded silicon-on-insulator (SOI) wafers in order to evaluate the quality of the starting material from different vendors and to monitor the degradation of lifetime during processing of the wafers. The goal of the investigation was to determine a correlation between the carrier lifetime of the SOI layer of the starting material and the output of the devices fabricated on the same wafer. Bonded SOI wafers from three different vendors were evaluated by a KOBELCO LTA-1000EP semiconductor wafer lifetime measuring system in order to investigate the quality of device layer silicon for the fabrication of optoelectronic devices where carrier lifetime plays a dominant role. The salient feature of the measuring system is the availability of three lasers with different depth of penetration where one of the lasers penetrates only 1 /spl mu/m which is suitable for lifetime measurement of SOI layer. The wavelength of the three lasers were 523 nm, 904 nm and 1047 mn with penetration depths of about 1 /spl mu/m, 30 /spl mu/m and 500 /spl mu/m respectively. Measurements were conducted on both front and backside of the SOI wafers with three lasers to ensure the accuracy of the lifetime of the layer of interest. The repeatability of the measurement was excellent and was within 3%. Based on the measured carrier lifetime of the starting materials, SOI wafers from two vendors were selected for optoelectronic device fabrication. The lifetime map of each processed wafers was obtained and the measured short circuit current of the devices were found to correlate with the average carrier lifetime of the same wafers.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132940803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3-D numerical simulation of the pseudo-MOS transistor 伪mos晶体管的三维数值模拟
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634949
D. Munteanu, S. Cristoloveanu, E. Guichard
{"title":"3-D numerical simulation of the pseudo-MOS transistor","authors":"D. Munteanu, S. Cristoloveanu, E. Guichard","doi":"10.1109/SOI.1997.634949","DOIUrl":"https://doi.org/10.1109/SOI.1997.634949","url":null,"abstract":"The /spl Psi/-MOSFET stands as the unique method permitting a quick and rather complete evaluation of the electrical properties of SOI wafers prior to any device processing. The aim of this paper is to report, for the first time, 3-D numerical simulations which validate the method and show the optimum conditions for application and parameter extraction.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134379224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transient response after pulsed ionizing excitation of several buried oxides in fully-depleted SOI NMOS transistors 几种埋藏氧化物在全耗尽SOI NMOS晶体管中脉冲电离激发后的瞬态响应
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634925
Y. Rebours, V. Ferlet-Cavrois, O. Gruber, C. Raynaud, J. Pelloie
{"title":"Transient response after pulsed ionizing excitation of several buried oxides in fully-depleted SOI NMOS transistors","authors":"Y. Rebours, V. Ferlet-Cavrois, O. Gruber, C. Raynaud, J. Pelloie","doi":"10.1109/SOI.1997.634925","DOIUrl":"https://doi.org/10.1109/SOI.1997.634925","url":null,"abstract":"The purpose of this article is to study and compare the time-dependent response of different buried oxide (BOX) materials through the coupling effect in fully-depleted transistors. This can be achieved by separating the contribution of charge transport and trapping in the BOX from floating body effects in the silicon film. This new technique avoids any distortion of the BOX response induced by direct C(V) or threshold voltage measurements that require the application of high voltages. Results show a similar behavior of the studied BOX (SIMOX, UNIBOND), i.e. deep hole trapping and shallow electron traps.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121413690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of interface traps in SOI material SOI材料中界面陷阱的表征
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634934
K. Vanheusden, W. L. Warren, W. Shedd, R. Pugh, D. Fleetwood, J. Schwank, R. Devine
{"title":"Characterization of interface traps in SOI material","authors":"K. Vanheusden, W. L. Warren, W. Shedd, R. Pugh, D. Fleetwood, J. Schwank, R. Devine","doi":"10.1109/SOI.1997.634934","DOIUrl":"https://doi.org/10.1109/SOI.1997.634934","url":null,"abstract":"In SOI material, the presence of interface traps at the buried oxide layer interfaces has been demonstrated from electrical data. More recently, interface defects were identified at the buried oxide interfaces in SOI material. In this study we use heat treatment under high-vacuum (instead of an inert ambient such as Ar) as a tool to enhance the buried interface trap density in the SOI material. The results provide new insights into the microscopic, chemical, and electrical signature of these interface traps in SOI.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121445896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of thin film SOI material defect requirements for advanced circuit applications [DRAMs] 先进电路应用[dram]中薄膜SOI材料缺陷要求分析
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634966
M. Alles, S. Wilson, H. Hovel, W. Maszara, R. Dolan
{"title":"Analysis of thin film SOI material defect requirements for advanced circuit applications [DRAMs]","authors":"M. Alles, S. Wilson, H. Hovel, W. Maszara, R. Dolan","doi":"10.1109/SOI.1997.634966","DOIUrl":"https://doi.org/10.1109/SOI.1997.634966","url":null,"abstract":"As thin film SOI (TFSOI) moves from R&D to pilot production, demonstration of circuit yields is crucial. Understanding the required defect levels of the TFSOI starting materials for targeted applications is essential to material suppliers as well as IC manufacturers. Comparative analysis of defect levels in various TFSOI materials and their potential impact on circuit yields has been summarized. Many companies are working on correlation between circuits and material defect levels; however, this data can be process specific and tends to be of limited access. This work applies an enhanced version of Poisson's equation (commonly used to calculate yield vs. defect densities) to examine required defect levels for application of TFSOI to advanced devices. Discrete defects are analyzed including surface particles (light scattering centers, LSC), HF defects, silicon threading dislocations, and buried oxide (BOX) defects. Some measured material data is included to note the present status and highlight potential challenges in achieving required levels.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124061703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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