High performance dual-gate FD-SOI CMOS process with an ultra thin TiSi/sub 2/

Abstract

Summary form only given. We have developed a manufacturable FD-SOI 0.35 /spl mu/m CMOS process with an ultra thin TiSi/sub 2/ film. We obtained sheet resistance of 10 /spl Omega//sq. for N/sup +/ and P/sup +/ SOI diffusions, and saturation current of 1.8 mA and 0.56 mA for NMOS and PMOS transistors (V/sub D/=V/sub G/=1.5 V, W=10 /spl mu/m), respectively. The feasibility of the process has been verified successfully by fabricating a 128 kbit SRAM.