Screening SOI substrates for radiation resistant space electronics applications

Total device isolation, speed, density, and radiation hardness (SEU) are significant advantages of silicon-on-insulator (SOI) substrates over bulk Si substrates. Taking advantage of these properties, we have been manufacturing partially depleted SOI/CMOS VLSI SRAMs (256K and 1M) and high density digital ASIC (>400K usable gates) chips for space electronics application in radiation harsh environments using full dose SIMOX (1.7-1.8/spl times/10/sup 18/ cm/sup -2/ dose at 190-200 keV) materials for some time. The full dose SIMOX wafers have been supplied with and without oxide caps from the manufacturers. The thickness of the top silicon and the thickness of the buried oxide after annealing are approximately 200-230 nm and 380 nm respectively. During the preparation of SIMOX wafers for production, practically all yield limiting issues of SIMOX technology were addressed: particles, HF defects, pipes (BOX pinholes), roughness, dislocations, thickness uniformity of top silicon and buried oxide, buried oxide pipes, Si islands in the buried oxide and unintentional background doping contamination on top silicon of the SOI materials. Poor functional yield has been correlated with particles on incoming materials. A nondestructive particle screening method was proposed and a database has been kept for every incoming SIMOX wafer. In addition, high standby currents were found to be associated with various defects (metallic contamination, dislocations, HF defects, buried oxide pipes, etc.) and unintentional impurity contamination.