{"title":"完全耗尽的设计标准-0.1 /spl mu/m SOI技术","authors":"J. Burns, R. Frankel, A. Soares, P. Wyatt","doi":"10.1109/SOI.1997.634941","DOIUrl":null,"url":null,"abstract":"A sub-0.25 /spl mu/m fully depleted silicon-on-insulator (FDSOI) technology has been developed and fully scaled ring oscillators fabricated using 193-nm lithography. This technology is being extended by incorporating phase shift techniques with 193-nm lithography to fabricate polysilicon gates with 0.1 /spl mu/m drawn channel lengths. The purpose of this paper is to define the process and design requirements for a fully depleted, 0.1 /spl mu/m SOI technology and predict the performance characteristics of 0.1 /spl mu/m ring oscillators.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design criteria for a fully depleted-0.1 /spl mu/m SOI technology\",\"authors\":\"J. Burns, R. Frankel, A. Soares, P. Wyatt\",\"doi\":\"10.1109/SOI.1997.634941\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A sub-0.25 /spl mu/m fully depleted silicon-on-insulator (FDSOI) technology has been developed and fully scaled ring oscillators fabricated using 193-nm lithography. This technology is being extended by incorporating phase shift techniques with 193-nm lithography to fabricate polysilicon gates with 0.1 /spl mu/m drawn channel lengths. The purpose of this paper is to define the process and design requirements for a fully depleted, 0.1 /spl mu/m SOI technology and predict the performance characteristics of 0.1 /spl mu/m ring oscillators.\",\"PeriodicalId\":344728,\"journal\":{\"name\":\"1997 IEEE International SOI Conference Proceedings\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.1997.634941\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1997.634941","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design criteria for a fully depleted-0.1 /spl mu/m SOI technology
A sub-0.25 /spl mu/m fully depleted silicon-on-insulator (FDSOI) technology has been developed and fully scaled ring oscillators fabricated using 193-nm lithography. This technology is being extended by incorporating phase shift techniques with 193-nm lithography to fabricate polysilicon gates with 0.1 /spl mu/m drawn channel lengths. The purpose of this paper is to define the process and design requirements for a fully depleted, 0.1 /spl mu/m SOI technology and predict the performance characteristics of 0.1 /spl mu/m ring oscillators.
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