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1997 IEEE International SOI Conference Proceedings最新文献

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1.3 /spl mu/m CMOS technology merged with 90 V HG-DMOS on SOI substrate 1.3 /spl mu/m CMOS技术与SOI衬底上90v HG-DMOS融合
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634938
T. Ohyanagi, A. Watanabe
{"title":"1.3 /spl mu/m CMOS technology merged with 90 V HG-DMOS on SOI substrate","authors":"T. Ohyanagi, A. Watanabe","doi":"10.1109/SOI.1997.634938","DOIUrl":"https://doi.org/10.1109/SOI.1997.634938","url":null,"abstract":"Summary form only given. The utilization of SOI substrates for Power Integrated Circuits (PICs) is a promising solution for the accumulation of circuits, because a circuit can be more compact due to its smaller isolation space. However, to our knowledge, on the market, the layout design rule for low-voltage (LV) CMOS on PICs goes up to 3 /spl mu/m. We report that 1.3 /spl mu/m CMOS technology can be merged with high-voltage (HV) MOS transistors on one chip. Achieving high drive ability and low power dissipation, High voltage Gate-Double diffusion MOS (HG-DMOS) transistors are introduced on our PICs. This is succeeded by our original two layer polysilicon gate-one having a thin gate oxide (/spl sim/ 250 /spl Aring/) and the other having a thick gate oxide (/spl sim/2300 /spl Aring/)-process.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125435588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quality of SOI film after surface smoothing with hydrogen annealing, touch-polishing 表面经过氢退火、触摸抛光后的SOI膜质量
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634967
W. Maszara, C. Gondran, S. Jackett-Murphy, P. Vasudev, S. S. Iyer, M. Anc
{"title":"Quality of SOI film after surface smoothing with hydrogen annealing, touch-polishing","authors":"W. Maszara, C. Gondran, S. Jackett-Murphy, P. Vasudev, S. S. Iyer, M. Anc","doi":"10.1109/SOI.1997.634967","DOIUrl":"https://doi.org/10.1109/SOI.1997.634967","url":null,"abstract":"We have conducted an investigation to evaluate the impact of both touch-polish and hydrogen annealing at different temperatures on the roughness, on the SOI film removal, as well as the impact of so processed surface on the integrity of gate oxide thermally grown on it, for SIMOX and BESOI material.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114576534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high speed offset-compensated differential comparator in floating body CMOS SOS technology for radiation hard switched-capacitor systems 一种用于辐射硬开关电容系统的高速偏置补偿式浮体CMOS SOS技术差分比较器
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634982
C. F. Edwards, W. Redman-White, M. Bracey
{"title":"A high speed offset-compensated differential comparator in floating body CMOS SOS technology for radiation hard switched-capacitor systems","authors":"C. F. Edwards, W. Redman-White, M. Bracey","doi":"10.1109/SOI.1997.634982","DOIUrl":"https://doi.org/10.1109/SOI.1997.634982","url":null,"abstract":"In this paper we describe how a high performance analogue cell has been designed and simulated using a SOS SPICE model, and successfully fabricated in a 1.5 /spl mu/m floating body SOS technology. The cell described here is a clocked comparator; this is a fundamental building block for realising high performance analogue-to-digital conversion in any technology. To achieve high tolerance to floating body effects, as well as radiation-induced bias and offset degradation, it is necessary to adopt highly specific design techniques to ensure performance is delivered.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129972957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparison of charge injection in SOI and bulk MOS analog switches SOI和MOS模拟开关中电荷注入的比较
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634954
L. Demeus, D. Flandre
{"title":"Comparison of charge injection in SOI and bulk MOS analog switches","authors":"L. Demeus, D. Flandre","doi":"10.1109/SOI.1997.634954","DOIUrl":"https://doi.org/10.1109/SOI.1997.634954","url":null,"abstract":"Summary form only given. The analog MOS switch is one of the major building blocks in switched-data circuits (switched capacitor, current-copier, track-and-hold, etc.). Their main limitation regarding accuracy is linked to the problem of charge injection that induces output voltage errors. Several physical studies recently addressed the charge injection problem in bulk MOSFETs under low-voltage conditions (considering the weak inversion contribution) or in SOI MOSFETs under large voltage transients. In this paper we compare charge injection in bulk and SOI MOS switches from a low-voltage circuit point of view, using MEDICI 2-D simulations, for three different MOS processes: typical bulk with a threshold voltage (VT) of 0.72 V, comparable fully-depleted SOI with VT=0.74 V, and low-voltage SOI. Our analysis has demonstrated significant differences in the charge components injected by bulk and SOI MOS switches and their dependence on process and circuit conditions. In carefully optimized circuits, low-voltage fully depleted SOI MOS switches may inject much less charges than in bulk and enable better compensation results.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Radiation hardened SOI CMOS and 1M SRAM 抗辐射SOI CMOS和1M SRAM
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634988
P. Fechner, G.D. Dougal, J. G. Sullwold, R. Swanson, G. Shaw, S.T. Liu, C. Yue
{"title":"Radiation hardened SOI CMOS and 1M SRAM","authors":"P. Fechner, G.D. Dougal, J. G. Sullwold, R. Swanson, G. Shaw, S.T. Liu, C. Yue","doi":"10.1109/SOI.1997.634988","DOIUrl":"https://doi.org/10.1109/SOI.1997.634988","url":null,"abstract":"Describes 2M rad(SiO/sub 2/) radiation hardened partially depleted SOI CMOS technology used to fabricate a 1M SRAM on full dose SIMOX (Separation by IMplantation of OXygen) wafers with an oxygen ion dose of 1.7/spl times/10/sup 18//cm/sup 2/ at 190 keV. They were annealed by Honeywell at 1325 /spl deg/C resulting in buried oxide thickness of approximately 370 nm and post CMOS processing silicon thickness of approximately 190 nm. Prior to processing, the SIMOX wafers are screened to achieve surface defect density of <0.2 per cm/sup 2/, HF defect density of <1 per cm/sup 2/, and background doping of <2/spl times/10/sup 16/ per cm/sup 3/.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122979908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ADVANTOX/sup TM/ more radiation-resistant than full dose SIMOX ADVANTOX/sup TM/比全剂量SIMOX更耐辐射
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634976
S.T. Liu, H. Hughes, W. Jenkins, L. Allen
{"title":"ADVANTOX/sup TM/ more radiation-resistant than full dose SIMOX","authors":"S.T. Liu, H. Hughes, W. Jenkins, L. Allen","doi":"10.1109/SOI.1997.634976","DOIUrl":"https://doi.org/10.1109/SOI.1997.634976","url":null,"abstract":"Summary form only given. Silicon-On-Insulator (SOI) material has received significant attention due to its ability to provide high performance and power reduction advantages attributable to reduced parasitic substrate capacitance and total oxide isolation of CMOS devices. SOI CMOS technology is now being considered as one of the most promising candidates for high speed and low power digital ULSI circuit applications. We have been producing radiation hard SOI SRAMs and ASICs using full dose SIMOX for some time. We have observed that the incoming full dose SIMOX material needs to be screened for production due to particulates and background impurity. In a search for quality SOI wafers at lower cost for future radiation hard electronics applications, we have evaluated a new low dose SIMOX called ADVANTOX/sup TM/. This paper reports the total dose radiation response of ADVANTOX/sup TM/ buried oxide, compares it to full dose SIMOX, and models the radiation response using a simple equation with two parameters.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"2022 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125874464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high density circular-shape SOI iMEMS with intelligent pressure sensor 一种具有智能压力传感器的高密度圆形SOI iMEMS
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634930
M.M.-O. Lee, Yang-Ho Moon
{"title":"A high density circular-shape SOI iMEMS with intelligent pressure sensor","authors":"M.M.-O. Lee, Yang-Ho Moon","doi":"10.1109/SOI.1997.634930","DOIUrl":"https://doi.org/10.1109/SOI.1997.634930","url":null,"abstract":"This paper presents an SOI iMEMS intelligent pressure sensor operation on a circular-shape diaphragm and its design which involves determining the target position for placing the transducer on the diaphragm through stress analyses based on various dimensional SOI structures along with a bulk Si one, including thermal residual stresses. Further, it proposes a way of integrating the sensor macros with a microprocessor as a monolithic chip solution. Piezoresistance in silicon is changed by conductivity of a material in response to an applied stresses on various structures at maximum stress point at various pressures. Based on transducer analysis, the sensitivity parameters for the transducer operation and their limiting factors are concisely summarized, where simulated results for the normal and shear stresses with piezoresistance coefficients are given.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance evaluation of bulk Si and SOI RF LDMOSFETs for emerging RFIC applications 用于新兴RFIC应用的块体Si和SOI RF ldmosfet的性能评估
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634956
P. Perupalli, M. Trivedi, K. Shenai, S. K. Leong
{"title":"Performance evaluation of bulk Si and SOI RF LDMOSFETs for emerging RFIC applications","authors":"P. Perupalli, M. Trivedi, K. Shenai, S. K. Leong","doi":"10.1109/SOI.1997.634956","DOIUrl":"https://doi.org/10.1109/SOI.1997.634956","url":null,"abstract":"This paper presents the evaluation of performance of 50 V LDMOSFETS designed in bulk Si and SOI for use in power amplifiers for cellular base stations. SOI technology has been fast emerging as the major technology for RF applications due to its inherent advantages such as lower parasitics, lower on-resistance and better noise immunity. Extensive 2-D simulations on an advanced process and device simulator have been performed to study the carrier dynamics in the LDMOSFET. This allows for a better understanding of the means to reduce the device parasitics, that are a major factor limiting the RF performance of the transistor. A simple circuit model has been developed for the LDMOSFET for use in performing large signal AC analyses for RF characterization. Non-Isothermal simulations on the SOI device have shown that at the feature dimensions under consideration, the self heating does not affect the DC and RF performance significantly.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115951602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A comparison of oxidation induced stress and defectivity in SIMOX and bonded SOI wafers SIMOX和结合SOI晶圆中氧化诱导应力和缺陷的比较
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634968
M. Mendicino, I. Yang, N. Cave, S. Veeraraghavan, P. Gilbert
{"title":"A comparison of oxidation induced stress and defectivity in SIMOX and bonded SOI wafers","authors":"M. Mendicino, I. Yang, N. Cave, S. Veeraraghavan, P. Gilbert","doi":"10.1109/SOI.1997.634968","DOIUrl":"https://doi.org/10.1109/SOI.1997.634968","url":null,"abstract":"We have shown that the trench liner oxidation step in Mesa or shallow trench isolation can affect stress in active Si areas. Significant differences in the response to that stress were observed between SIMOX and Bonded SOI wafers. Our results indicate that a threshold for stress relaxation exists in trench-isolated structures which is much larger for Bonded SOI wafers than for SIMOX with T/sub BOX/=3700 /spl Aring/.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127155064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Physical background of hot-carrier-induced abnormal gm degradation in a sub-0.1-/spl mu/m-channel nMOSFETs/SIMOX with an LDD structure LDD结构下0.1-/spl μ /m沟道nmosfet /SIMOX中热载子诱导异常gm降解的物理背景
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634950
Y. Omura
{"title":"Physical background of hot-carrier-induced abnormal gm degradation in a sub-0.1-/spl mu/m-channel nMOSFETs/SIMOX with an LDD structure","authors":"Y. Omura","doi":"10.1109/SOI.1997.634950","DOIUrl":"https://doi.org/10.1109/SOI.1997.634950","url":null,"abstract":"This paper describes hot-carrier-induced abnormal g/sub m/ degradation in 0.04-/spl mu/m-channel nMOSFETs/SIMOX, which is not easily predicted, and its physical background.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126972479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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