A high speed offset-compensated differential comparator in floating body CMOS SOS technology for radiation hard switched-capacitor systems

Abstract

In this paper we describe how a high performance analogue cell has been designed and simulated using a SOS SPICE model, and successfully fabricated in a 1.5 /spl mu/m floating body SOS technology. The cell described here is a clocked comparator; this is a fundamental building block for realising high performance analogue-to-digital conversion in any technology. To achieve high tolerance to floating body effects, as well as radiation-induced bias and offset degradation, it is necessary to adopt highly specific design techniques to ensure performance is delivered.