1997 IEEE International SOI Conference Proceedings最新文献

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Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects 考虑边壁相关窄通道效应的台面隔离全耗尽超薄SOI NMOS器件的紧凑电流模型
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634944
J. Kuo, K. Su
{"title":"Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects","authors":"J. Kuo, K. Su","doi":"10.1109/SOI.1997.634944","DOIUrl":"https://doi.org/10.1109/SOI.1997.634944","url":null,"abstract":"This paper presents the sidewall-related narrow channel effects on the current conduction in mesa-isolated fully-depleted ultra-thin SOI NMOS devices. As verified by the 3D simulation results, the dosed-form analytical model predicts that in the subthreshold region the channel current near the sidewall dominates due to narrow channel effects.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131244485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An alternative gate electrode material of fully depleted SOI CMOS for low power applications 用于低功耗应用的完全耗尽SOI CMOS栅极替代材料
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634912
T. Hsiao, A.W. Wang, K. Saraswat, J. Woo
{"title":"An alternative gate electrode material of fully depleted SOI CMOS for low power applications","authors":"T. Hsiao, A.W. Wang, K. Saraswat, J. Woo","doi":"10.1109/SOI.1997.634912","DOIUrl":"https://doi.org/10.1109/SOI.1997.634912","url":null,"abstract":"Summary form only given. In this work, a variable gate work-function scheme was proposed, using a p/sup +/ polycrystalline SiGe/Si stack gate. The Ge composition is varied to achieve the desired threshold voltage while giving latitude in channel doping. Using this work-function engineering, a threshold voltage of 0.2 to 0.6 V can be easily obtained for sub-0.25 /spl mu/m devices fabricated on ultra-thin film SOI. This technology can achieve near-symmetric threshold voltages for NMOS and PMOS devices with near-symmetric moderate channel doping concentration. This scalable gate work-function engineering can be an integral part of deep submicron SOI CMOS design and promises to achieve superior performance for low power electronics.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114528816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Effect of H/sub 2/ annealing on silicon quality and 1/f noise in SOS H/sub / 2/退火对SOS中硅质量和1/f噪声的影响
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634977
T. Morishita, Y. Moriyasu, Y. Kawakami, M. Matsui, T. Kobayashi, M. Kimura, R. Reedy
{"title":"Effect of H/sub 2/ annealing on silicon quality and 1/f noise in SOS","authors":"T. Morishita, Y. Moriyasu, Y. Kawakami, M. Matsui, T. Kobayashi, M. Kimura, R. Reedy","doi":"10.1109/SOI.1997.634977","DOIUrl":"https://doi.org/10.1109/SOI.1997.634977","url":null,"abstract":"In this work, we have investigated silicon surface defect of SOS that had been subjected to H/sub 2/ annealing at temperature ranging from 900/spl deg/C to 1150/spl deg/C by means of SEM. We have also investigated the effects of the surface defect density on l/f noise of n-MOSFET.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121888716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SOI materials defect characterization SOI材料缺陷表征
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634974
D. Pham, B. Nguyen, D. O'meara, V. Wang, N. Nguyen, J. Smith, J. Veteran, M. Mendicino, A. Campbell
{"title":"SOI materials defect characterization","authors":"D. Pham, B. Nguyen, D. O'meara, V. Wang, N. Nguyen, J. Smith, J. Veteran, M. Mendicino, A. Campbell","doi":"10.1109/SOI.1997.634974","DOIUrl":"https://doi.org/10.1109/SOI.1997.634974","url":null,"abstract":"In this study, the SOI wafers made by various bonding or implant techniques were extensively characterized for physical defects using various metrologies such as optical, X-ray, electron microscopy and SIMS. Defect characterization was performed as received from vendors and after thinning the SOI layer by oxidation and oxide removal.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low temperature Si layer splitting 低温硅层分裂
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634965
Q. Tong, T. Lee, L. Huang, Y. Chao, U. Gosele
{"title":"Low temperature Si layer splitting","authors":"Q. Tong, T. Lee, L. Huang, Y. Chao, U. Gosele","doi":"10.1109/SOI.1997.634965","DOIUrl":"https://doi.org/10.1109/SOI.1997.634965","url":null,"abstract":"Wafer bonding opens up new design possibilities for the fabrication of various single crystalline semiconductor on insulator (SOI) materials. SOI has been realized by layer splitting (\"smart-cut\"). However, except in the cases where only a small difference in the thermal expansion coefficients between the Si and the substrates is present, other SOI material combinations usually suffer from excessive thermal stresses due to thermal mismatch between the Si and the dissimilar substrates during annealing before layer splitting. For SOQ (Si on Quartz), at room temperature the thermal expansion coefficient of Si is 2.56/spl times/10/sup -6///spl deg/C while that of synthetic quartz is only 0.5/spl times/10/sup -6///spl deg/C. A bonded 4\" standard Si/quartz pair (both of /spl sim/525 /spl mu/m in thickness), will typically crack at /spl sim/180/spl deg/C. Since the splitting temperature in the smart-cut process exceeds 500/spl deg/C, the Si wafer in the Si/quartz pair has to be thinned down sufficiently (<150 /spl mu/m) to avoid cracking of the bonded pair during the Si layer splitting. However, a main advantage offered by the smart cut method is lost, namely that extensive lapping and etching to remove most of the substrate is avoided and the substrate from which the Si layer is transferred can be reused. In order to preserve these advantages a smarter-cut approach which employes a low temperature Si layer splitting technology is described.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126133623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hot-carrier-induced degradation in deep submicron Unibond and SIMOX MOSFETs 热载流子诱导的深亚微米单键和SIMOX mosfet的降解
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634975
S. Renn, C. Raynaud, J. Pelloie, F. Balestra
{"title":"Hot-carrier-induced degradation in deep submicron Unibond and SIMOX MOSFETs","authors":"S. Renn, C. Raynaud, J. Pelloie, F. Balestra","doi":"10.1109/SOI.1997.634975","DOIUrl":"https://doi.org/10.1109/SOI.1997.634975","url":null,"abstract":"SOI devices are greatly competitive for the ULSI era due to significantly improved electrical properties compared with bulk devices. However, when the gate length is shortened in the deep submicron range, SOI MOSFETs also suffer from severe hot-carrier-induced degradations. Especially, for fully depleted (FD) thin film SOI devices, stressing the front channel may also damage the back channel, and the threshold voltage (Vt) shift may be affected by the charges trapped in the opposite oxide owing to the interface-coupling effect. It has been reported that the back interface of FD P-channel SIMOX transistor degrades much more than the front interface, due to the poor electrical properties of the back buried oxide. A new SOI material technology \"Smart-cut\" has been recently developed for the fabrication of Unibond wafers. A good uniformity of silicon layer without any defects and a very sharp bonded interface have been obtained from this technology. Therefore, the aim of this paper is to present a thorough comparison on hot-carrier-induced degradation in deep submicron thin Unibond and SIMOX MOSFETs.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116102410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Creation of SiGe-based SIMOX structures by low energy oxygen implantation 低能氧注入制备sig基SIMOX结构
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634910
Y. Ishikawa, T. Saito, N. Shibata, S. Fukatsu
{"title":"Creation of SiGe-based SIMOX structures by low energy oxygen implantation","authors":"Y. Ishikawa, T. Saito, N. Shibata, S. Fukatsu","doi":"10.1109/SOI.1997.634910","DOIUrl":"https://doi.org/10.1109/SOI.1997.634910","url":null,"abstract":"Summary form only given. An ultra thin, dislocation-free, SiGe virtual substrate on SiO/sub 2/ has been demonstrated as a new class of SOI structure by using low energy oxygen implantation. SIMOX-based virtual substrates are expected to boost the electronic as well as optoelectronic potentials of Si/SiGe.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance of /spl gamma/-irradiated gate-all-around SOI MOS OTA amplifiers /spl γ辐照栅极全能SOI MOS OTA放大器的性能
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634933
A. Vandooren, P. Francis, D. Flandre, J. Colinge
{"title":"Performance of /spl gamma/-irradiated gate-all-around SOI MOS OTA amplifiers","authors":"A. Vandooren, P. Francis, D. Flandre, J. Colinge","doi":"10.1109/SOI.1997.634933","DOIUrl":"https://doi.org/10.1109/SOI.1997.634933","url":null,"abstract":"Gate-All-Around SOI MOSFETs are very promising for the fabrication of ultra rad-hard circuits. The specific structure of the GAA device allows to combine radiation hardness and the great technological potential of SOI technology, e.g. for low-voltage low-power or high temperature circuits. Up to now only few studies have been realized on rad-hard GAA analog circuits. Present work discusses the performances of GAA SOI Operational Transconductance Amplifier (OTA) implementations under /spl gamma/-rays irradiation. The main OTA parameters, i.e. DC open-loop gain and gain-bandwidth product, have been investigated and correlated to the evolution of the Early voltage and the scaled transconductance of individual devices. The experiments were performed up to a total dose of 15 Mrad(Si) on two OTA architectures.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130646774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficacy of body ties under dynamic switching conditions in partially depleted SOI CMOS technology 部分耗尽SOI CMOS技术中动态开关条件下体链的效率
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634972
S. Krishnan
{"title":"Efficacy of body ties under dynamic switching conditions in partially depleted SOI CMOS technology","authors":"S. Krishnan","doi":"10.1109/SOI.1997.634972","DOIUrl":"https://doi.org/10.1109/SOI.1997.634972","url":null,"abstract":"Historically, body ties have been designed using removal of DC floating-body (FB) effects (e.g., kink, breakdown voltage) as the main criteria. It has been implicitly assumed that the transient FB effects would be minimized too with such a tie. However, such body ties while \"suppressing\" DC effects, may not necessarily be effective in AC/transient conditions, since the body (dis)charging time constants may be much larger than desired. For example, in a digital SOI CMOS circuit, with the gate switching at a few tens of ps, the efficacy of the body tie may be little or none at all, depending on the response time /spl tau//sub B/(=R/sub B/C/sub B/) of the body. Hence, in order to design effective body ties in transients, dynamic (dis)charging effects due to R/sub B/ and C/sub B/ in the body must be included.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133562142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High speed SOI buffer circuit with the efficient connection of subsidiary MOSFETs for dynamic threshold control 高速SOI缓冲电路,有效连接辅助mosfet进行动态阈值控制
1997 IEEE International SOI Conference Proceedings Pub Date : 1997-10-06 DOI: 10.1109/SOI.1997.634978
Jong-Ho Lee, Young-June Park
{"title":"High speed SOI buffer circuit with the efficient connection of subsidiary MOSFETs for dynamic threshold control","authors":"Jong-Ho Lee, Young-June Park","doi":"10.1109/SOI.1997.634978","DOIUrl":"https://doi.org/10.1109/SOI.1997.634978","url":null,"abstract":"Summary form only given. We propose a new non-inverting SOI buffer circuit adopting dynamic body bias control via subsidiary MOSFETs connected efficiently to obtain high speed at low supply voltage. Device simulation has been performed to show current derivability of body controlled devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of SOI CMOS buffer circuit. Delay time reduction of the SOI buffer circuit over conventional SOI CMOS buffer circuit with same area is about 36% at V/sub s/=1.2 V and C/sub L/=2 pF.","PeriodicalId":344728,"journal":{"name":"1997 IEEE International SOI Conference Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133508810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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