1.3 /spl mu/m CMOS technology merged with 90 V HG-DMOS on SOI substrate

Summary form only given. The utilization of SOI substrates for Power Integrated Circuits (PICs) is a promising solution for the accumulation of circuits, because a circuit can be more compact due to its smaller isolation space. However, to our knowledge, on the market, the layout design rule for low-voltage (LV) CMOS on PICs goes up to 3 /spl mu/m. We report that 1.3 /spl mu/m CMOS technology can be merged with high-voltage (HV) MOS transistors on one chip. Achieving high drive ability and low power dissipation, High voltage Gate-Double diffusion MOS (HG-DMOS) transistors are introduced on our PICs. This is succeeded by our original two layer polysilicon gate-one having a thin gate oxide (/spl sim/ 250 /spl Aring/) and the other having a thick gate oxide (/spl sim/2300 /spl Aring/)-process.