Design criteria for a fully depleted-0.1 /spl mu/m SOI technology

Abstract

A sub-0.25 /spl mu/m fully depleted silicon-on-insulator (FDSOI) technology has been developed and fully scaled ring oscillators fabricated using 193-nm lithography. This technology is being extended by incorporating phase shift techniques with 193-nm lithography to fabricate polysilicon gates with 0.1 /spl mu/m drawn channel lengths. The purpose of this paper is to define the process and design requirements for a fully depleted, 0.1 /spl mu/m SOI technology and predict the performance characteristics of 0.1 /spl mu/m ring oscillators.