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2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Application of Back-side Laser Technique on Failure Analysis 背面激光技术在失效分析中的应用
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378099
W. Hoe, R. Lin, C. H. Chong, Coswin Lin
{"title":"Application of Back-side Laser Technique on Failure Analysis","authors":"W. Hoe, R. Lin, C. H. Chong, Coswin Lin","doi":"10.1109/IPFA.2007.4378099","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378099","url":null,"abstract":"The application of backside emission and laser technique (TIVA/OBIRCH) had been widely used in the semiconductor industry. This paper will discuss the usage of backside laser damage method to aid in this technique on localizing the failure spot. Two applications on backside laser; 1.Memory scramble verification and 2. Yield loss scenario using backside laser to verify the failure hypothesis will also be discussed.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123352347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Proof-of-Concept Structure for Investigation of Successive Soft Gate Oxide Breakdowns in Two Dimensions 二维连续软栅氧化击穿研究的概念验证结构
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378063
B. Kaczer, R. Fernández, A. Nackaert, T. Chiarella, G. Groeseneken
{"title":"Proof-of-Concept Structure for Investigation of Successive Soft Gate Oxide Breakdowns in Two Dimensions","authors":"B. Kaczer, R. Fernández, A. Nackaert, T. Chiarella, G. Groeseneken","doi":"10.1109/IPFA.2007.4378063","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378063","url":null,"abstract":"In this paper we describe a structure designed and fabricated for the purpose of locating successive SBD's in 2D. It is shown that the original BD location method can be readily extended to 2D, for both accumulation (Degraeve et al., 2001) and inversion (Crupi et al., 2005). It is concluded that the locations of two successive SBD's can be readily distinguished and that subsequent SBD events do not appear to be correlated within the analysis of this work. Limitations in downscaling the structure are also discussed.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123767102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
EBIC Investigations on Active Polymer Devices 有源聚合物器件的EBIC研究
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378088
A. Pugatschow, R. Heiderhoff, M. Forster, U. Scherf, L. Balk
{"title":"EBIC Investigations on Active Polymer Devices","authors":"A. Pugatschow, R. Heiderhoff, M. Forster, U. Scherf, L. Balk","doi":"10.1109/IPFA.2007.4378088","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378088","url":null,"abstract":"For the first time, EBIC microscopy is applied for investigations on active polymer devices, OFETs with TPA-Dimethyl and P3HT polymers as active layers. The internal electrical field distributions of these devices are characterized in dependence on biasing conditions. Poole-Frenkel field dependences at source and drain contacts are demonstrated.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123545285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ESD protection for sub-45 nm MugFET technology 45纳米以下MugFET技术的ESD保护
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378077
M. Natarajan, S. Thijs, D. Trémouilles, D. Linten, N. Collaert, M. Jurczak, G. Groeseneken
{"title":"ESD protection for sub-45 nm MugFET technology","authors":"M. Natarajan, S. Thijs, D. Trémouilles, D. Linten, N. Collaert, M. Jurczak, G. Groeseneken","doi":"10.1109/IPFA.2007.4378077","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378077","url":null,"abstract":"From the design point of view, while such technology options may result in increased transistor performance, the ability to achieve sufficient product reliability is to be addressed. Among the industry accepted reliability requirements, electrostatic discharge (ESD) reliability assessment is the focus of this work.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124840668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ensuring IC Reliability by Automated Design Checks 通过自动设计检查确保IC可靠性
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378083
P. Chawda, M. Rajeswaran, J. Joy, P. R. Suresh
{"title":"Ensuring IC Reliability by Automated Design Checks","authors":"P. Chawda, M. Rajeswaran, J. Joy, P. R. Suresh","doi":"10.1109/IPFA.2007.4378083","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378083","url":null,"abstract":"This paper describes a schematic tool for verification of voltage levels of the signal and power nets to ensure the reliability of devices in the complex designs. The tool traces voltage levels of all nets/devices from the primary I/O pins of full chip and flags wrong voltage levels for power and signal nets in IC designs. The checker increases the efficiency of designers while creating/verifying the schematic.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126211676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Failure Mode Investigation of Barrier Layer TaN Combined with Al Pad Architecture using in Cu Process 阻挡层TaN结合Al衬垫结构在Cu工艺中的失效模式研究
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378097
Po-Ying Chen, Shen-Li Chen, M. Tsai, M.H. Jing, T. Lin
{"title":"The Failure Mode Investigation of Barrier Layer TaN Combined with Al Pad Architecture using in Cu Process","authors":"Po-Ying Chen, Shen-Li Chen, M. Tsai, M.H. Jing, T. Lin","doi":"10.1109/IPFA.2007.4378097","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378097","url":null,"abstract":"CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called \"cosmetic defects\" in 130- and 90-nm complementary metal-oxide-semiconductor (CMOS) process node.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of Time-Dependent Dielectric Breakdown on Gate Oxide Capacitors at High Temperature 栅极氧化物电容器高温下随时间介电击穿的研究
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378103
R. Moonen, P. Vanmeerbeek, G. Lekens, W. De Ceuninck, P. Moens, J. Boutsen
{"title":"Study of Time-Dependent Dielectric Breakdown on Gate Oxide Capacitors at High Temperature","authors":"R. Moonen, P. Vanmeerbeek, G. Lekens, W. De Ceuninck, P. Moens, J. Boutsen","doi":"10.1109/IPFA.2007.4378103","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378103","url":null,"abstract":"Thin layers of silicon dioxide used as a dielectric for capacitors or as the gate oxide for a MOS semiconductor device are subject to a wear-out mechanism known as time- dependent dielectric breakdown (TDDB). This physical failure mechanism has always been of notable reliability matter in semiconductor industry because of the incessant tendency towards smaller devices. In this paper, the intrinsic oxide lifetime of 7.2 nm gate oxide capacitors (n-type) has been studied in, a wide electric field ranging from 8.3 to 13.2 MV/cm at high temperatures (up to 240degC). By means of a high resolution/high speed TDDB measurement technique, we performed TDDB tests with constant voltage stress (CVS) at different stress conditions of temperature and voltage. We particularly concentrated on the high temperature aspect of TDDB to answer the demands of new smart power technologies (Tjunc up to 225degC). It was found that the intrinsic oxide breakdown mechanism perfectly matches the anode hole injection (AHI) model (1/EOX model) at these high temperatures. In summary, this physical model is most convenient to extrapolate the intrinsic oxide lifetime from accelerated tests to normal at-use conditions.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132008173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Experimental Study of Charge Displacement in Nitride Layer and its Effect on Threshold Voltage Instability of Advanced Flash Memory Devices 氮化层电荷位移及其对先进闪存器件阈值电压不稳定性影响的实验研究
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378061
G. Tao, S. Nath, C. Ouvrard, H. Chauveau, D. Dormans, R. Verhaar
{"title":"Experimental Study of Charge Displacement in Nitride Layer and its Effect on Threshold Voltage Instability of Advanced Flash Memory Devices","authors":"G. Tao, S. Nath, C. Ouvrard, H. Chauveau, D. Dormans, R. Verhaar","doi":"10.1109/IPFA.2007.4378061","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378061","url":null,"abstract":"The effect of charge displacement in nitride layer of ONO stack in scaled flash cells are experimentally studied by using gate stress measurements. The redistribution of charge is found to follow Poole-Frenkel conduction mechanisms. However, the measurements on scaled devices show significant random telegraph noise. The noise will be even more pronounced in future scaled devices.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116795496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparison of Digital- and Analog-like Progressive Breakdown in nMOSFETs and pMOSFETs with Ultrathin Gate Oxide 超薄栅极氧化物nmosfet和pmosfet的数字和模拟渐进击穿比较
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378082
V. Lo, S. Ashwin, K. Pey, C. Tung
{"title":"Comparison of Digital- and Analog-like Progressive Breakdown in nMOSFETs and pMOSFETs with Ultrathin Gate Oxide","authors":"V. Lo, S. Ashwin, K. Pey, C. Tung","doi":"10.1109/IPFA.2007.4378082","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378082","url":null,"abstract":"The gate leakage current (Ig) evolution during progressive breakdown (PBD) in both n- and p-channel metal-oxide- semiconductor field-effect transistors (n/pMOSFETs) with ultrathin gate oxide is studied using a multiple-stage constant-voltage stress. Our results reveal that mechanisms responsible for the early stage of PBD in both types of transistors could be universal, but different mechanisms could be involved in controlling the later stage of PBD. This finding provides more insights in understanding the variation of power-law exponent (40-50 for nMOSFETs, and 33-45 for pMOSFETs) reported in Ref. [1].","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel Flip-Chip Probing Methodology Using Electron Beam Probing 利用电子束探测的新型倒装芯片探测方法
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378054
R. Jain, T. Malik, T. Lundquist, R. Schlangen, R. Leihkauf, U. Kerst, C. Boit
{"title":"Novel Flip-Chip Probing Methodology Using Electron Beam Probing","authors":"R. Jain, T. Malik, T. Lundquist, R. Schlangen, R. Leihkauf, U. Kerst, C. Boit","doi":"10.1109/IPFA.2007.4378054","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378054","url":null,"abstract":"The measurement of timing and voltage signals inside integrated circuits (IC) is critical to debugging new devices, to failure analysis of advanced devices, validating new IP (intellectual property) in new silicon, etc. E-beam probing (EBP) has been very useful for front side devices for over two decades. For measuring signals below the top metal layers, probe pads are made using a focused ion beam (FIB) where lower metal was accessible. Increasing migration of ICs to flip chip packaging has necessitated the need for a new tool set or methodology for design debug and failure analysis. This paper introduces data taken from a flip chip using an IDS 10K+ E-beam Prober (EBPr). The samples are thinned using an Allied HiTech polishing wheel and the Credence OptiFIB. The investigation utilized the capability of the EBPr to acquire both repeating (clocks) and non-repeating signals at various: supply voltages, loop lengths frequencies.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124560054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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