通过自动设计检查确保IC可靠性

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI:10.1109/IPFA.2007.4378083

P. Chawda, M. Rajeswaran, J. Joy, P. R. Suresh

{"title":"通过自动设计检查确保IC可靠性","authors":"P. Chawda, M. Rajeswaran, J. Joy, P. R. Suresh","doi":"10.1109/IPFA.2007.4378083","DOIUrl":null,"url":null,"abstract":"This paper describes a schematic tool for verification of voltage levels of the signal and power nets to ensure the reliability of devices in the complex designs. The tool traces voltage levels of all nets/devices from the primary I/O pins of full chip and flags wrong voltage levels for power and signal nets in IC designs. The checker increases the efficiency of designers while creating/verifying the schematic.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Ensuring IC Reliability by Automated Design Checks\",\"authors\":\"P. Chawda, M. Rajeswaran, J. Joy, P. R. Suresh\",\"doi\":\"10.1109/IPFA.2007.4378083\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a schematic tool for verification of voltage levels of the signal and power nets to ensure the reliability of devices in the complex designs. The tool traces voltage levels of all nets/devices from the primary I/O pins of full chip and flags wrong voltage levels for power and signal nets in IC designs. The checker increases the efficiency of designers while creating/verifying the schematic.\",\"PeriodicalId\":334987,\"journal\":{\"name\":\"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2007.4378083\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2007.4378083","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种在复杂设计中用于验证信号和电网电压水平的原理图工具，以确保设备的可靠性。该工具从全芯片的主I/O引脚跟踪所有网络/设备的电压水平，并标记IC设计中电源和信号网络的错误电压水平。检查器在创建/验证原理图时提高了设计人员的效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Ensuring IC Reliability by Automated Design Checks

This paper describes a schematic tool for verification of voltage levels of the signal and power nets to ensure the reliability of devices in the complex designs. The tool traces voltage levels of all nets/devices from the primary I/O pins of full chip and flags wrong voltage levels for power and signal nets in IC designs. The checker increases the efficiency of designers while creating/verifying the schematic.

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2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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