I. De Wolf, F. Duflos, B. Vandevelde, P. Vercruysse, D. Vanderstraeten
{"title":"Impact Induced Metal-Crush Failures","authors":"I. De Wolf, F. Duflos, B. Vandevelde, P. Vercruysse, D. Vanderstraeten","doi":"10.1109/IPFA.2007.4378086","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378086","url":null,"abstract":"The authors show for the first time that metal-crush failures can also be caused by mechanical impact which occurs during handling of the package and pick and place processes. So, not only thermo-mechanical effects might cause these failures. The paper also show a clear correlation between the observed failures on sample IC that returned from the field, and the failures observed on samples which were studied with the impact test. Both the position and the failure signature are the same. The author also showed that the sensitivity of packages for this failure cause highly depends on the chip coverage and that it is layout dependent. No die coating and polyimide coating show the best resistance against impact damage. Single and dual drop coatings are very sensitive. As such, die coat needs to be avoided as much as possible. However, since some designs count on its stress relieving ability to keep parameters within specification, the effectiveness of polyimide needs to be characterized. Moreover, it was found that this kind of impact can cause passivation cracks without causing an electrical failure of the chip, or even no failure after ATE test and after additional bake and solder reflow tests. The Charpy system is a representative tool for the evaluation of the robustness of packages within the logistic flow. The most effective activation stress test to combine with mini-Charpy tests still needs to be defined. This possible failure cause was up to now never investigated and never taken into account in the qualification process of packaging material. It is clear that the sensitivity of different packaging types and moulding components to such impact should be tested in advance and added to the qualification process. Finite element modelling clearly indicates that particle indentation is causing high tensile stresses in the passivation layer. These stresses are in the order of the ultimate stress values for these materials.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125043843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Q. Ngo, T. Yamada, K. Gleason, M. Suzuki, H. Kitsuki, A. Cassell, C. Yang
{"title":"Electrothermal Transport in Carbon Nanostructures","authors":"Q. Ngo, T. Yamada, K. Gleason, M. Suzuki, H. Kitsuki, A. Cassell, C. Yang","doi":"10.1149/1.3203987","DOIUrl":"https://doi.org/10.1149/1.3203987","url":null,"abstract":"Heat generation in carbon nanofibers (CNF) has raised concerns regarding reliability in these structures under high- current conditions. This work addresses the interplay between electron transport and resulting Joule heating in CNFs. The model relates current to power dissipation leading to temperature rise in the structure, thus elucidating the relationship between thermal and electrical properties in carbon nanostructures.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123246030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability- and Process-Variation Aware Design of VLSI Circuits","authors":"M. Alam, K. Kang, B. Paul, K. Roy","doi":"10.1109/IPFA.2007.4378050","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378050","url":null,"abstract":"We review the literature for reliability- and process-variation aware VLSI design to find that an exciting area of research/application is rapidly emerging as a core topic of IC design. Design of reliable circuits with unreliable component is a significant challenge that is likely to remain relevant for all circuit designs from now on, therefore any contribution in this field is likely to have lasting effect of the design philosophy of integrated circuits","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114140706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology","authors":"Shih-Hung Chen, M. Ker","doi":"10.1109/IPFA.2007.4378093","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378093","url":null,"abstract":"PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, turned-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114243990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Moore's Law: A CMOS Scaling Perspective","authors":"S. Tyagi","doi":"10.1109/IPFA.2007.4378049","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378049","url":null,"abstract":"In this paper we presented a retrospective on Moore's law, highlighting the salient feature of industry leading 65nm CMOS technology for high performance logic, and highlighted future challenges and approaches to overcome those.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"461 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129566829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Atomic Scale Strain Measurement for Nanoelectronic Devices","authors":"C. Tung, K. Pey, Fu Qinrong, B. Fox","doi":"10.1109/IPFA.2007.4378052","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378052","url":null,"abstract":"Atomic scale lattice strain measurement using high resolution transmission electron microscopic (HR- TEM) is an important application for semiconductor device characterization. Recent advancement and issues in these areas are discussed. Their potential applications in contemporary sub-45 nm metal-oxide- semiconductor field effect transistor (MOSFET) technology nodes are crucial. Major technical limitation in using these characterization techniques in wafer production environment is discussed and solution proposed.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127753264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In-Yao Lee, Tsung-Ping Hsu, W.W. Wang, Yi Chiu, H. Tang, Fan-Chung Tseng, K. Lee
{"title":"Failure Analysis of a MEMS Micro-Injector Printing Head","authors":"In-Yao Lee, Tsung-Ping Hsu, W.W. Wang, Yi Chiu, H. Tang, Fan-Chung Tseng, K. Lee","doi":"10.1109/IPFA.2007.4378068","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378068","url":null,"abstract":"The failure mechanism of a monolithic MEMS twin-bubble micro-injector failed to eject ink smoothly has been investigated. A model that analyzes the thermal expansion mismatch among the nozzle plate, the silicon substrate, and the PPO housing is proposed to explain the failure mechanism of the MEMS micro-injector printing head. In the proposed model, the thickness of nozzle plate and the width of manifold opening are the key parameters to achieve a robust design. When the gold layer thickness of nozzle plate is increased to 20 um, the robustness of the MEMS structure is improved substantially and no more ink ejection failures related to chamber crack of thermal stress is observed.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131794384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Statistical Analysis of Multi-Censored Electromigration Data using the EM Algorithm","authors":"N. Raghavan, C. Tan","doi":"10.1109/IPFA.2007.4378096","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378096","url":null,"abstract":"The novelty of this work lies in using the E&M algorithm for analyzing multi-censored mixture distribution EM data. Furthermore, the Akaike Information Criterion (AIC) will be used to determine the number of failure mechanisms in a given set of failure data and the Bayes' posterior probability theory is applied to determine the probability of each failure data belonging to the different failure mechanisms. All these useful information are further validated by performing failure analysis on selected test units.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133745445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Internal Photoemission Study on Reliability of Ultra-thin Zirconium Oxide Films on Strained-Si","authors":"M. Bera, C. Mahata, C. Maiti","doi":"10.1109/IPFA.2007.4378066","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378066","url":null,"abstract":"As scaling laws become less effective in boosting performance for CMOS devices for 90 nm and below, substrate- and process-induced strain engineering are playing an ever increasing role in performance enhancement. Strained-Si MOSFETs are also attractive for high speed and low power applications (Maiti et al., 2007). Ultra thin SiO2 gate dielectrics, of less than 1.5 nm in thickness, are needed for the 45 nm technology node and beyond. In order to reduce the leakage current, an extensive search for alternative high dielectric constant (high-k) gate materials that would probably replace the SiO2 for the sub-45 nm CMOS technologies is being pursued. In this article, we report for the first time, the results of the internal photoemission (IPE) study on reliability properties of microwave-plasma deposited high-k gate dielectric (ZrO2) films on strained-Si/SiGe heterolayers. The kinetics of charge trapping/detrapping and its chemical nature have been investigated through IPE and electron paramagnetic resonance study.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114417762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mechanism of Bias-Temperature Instability: Results from Positive Gate Stress","authors":"D. Ang, G. Du, S. Wang","doi":"10.1109/IPFA.2007.4378065","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378065","url":null,"abstract":"Hole trap generation under positive gate stressing of the ultra-thin oxynitride gate p-MOSFET is investigated. The experimental evidence is shown to be consistent with the hole trapping framework proposed for NBTI. Deep-level hole traps pinned by the Si-SiO2 conduction band discontinuity and the slow repassivation of Nit account for long-term device degradation. Generation of shallow hole traps is revealed via the increased Delta|V th| following a fast positive-negative-positive voltage ramp. The results offer potential insights into understanding the role of processing (e.g. plasma induced oxide damage) on the NBTI of the p-MOSFET.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126768933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}