M. Muhammad, R. Gauthier, K. Chatty, Junjun Li, C. Seguin
{"title":"Failure Analysis of I/O with ESD Protection Devices in Advanced CMOS Technologies","authors":"M. Muhammad, R. Gauthier, K. Chatty, Junjun Li, C. Seguin","doi":"10.1109/IPFA.2007.4378100","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378100","url":null,"abstract":"Many types of ESD protection devices such as diodes, NFETs, SCRs and RC-triggered power clamps having different failure mechanisms are used in advanced CMOS technologies. Circuit schematic analysis and SEM failure analysis are utilized to clearly predict and identify the failing I/O driver/receiver devices and/or the various ESD protection devices during an ESD event.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121253418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Chang, M. Ker, Tai-Xiang Lai, Tien-Hao Tang, K. Su
{"title":"The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process","authors":"W. Chang, M. Ker, Tai-Xiang Lai, Tien-Hao Tang, K. Su","doi":"10.1109/IPFA.2007.4378094","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378094","url":null,"abstract":"The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131825868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving the DC performance of Bulk FinFETs by Optimum Body Doping","authors":"C. R. Manoj, M. Nagpal, V. Ramgopal Rao","doi":"10.1109/IPFA.2007.4378080","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378080","url":null,"abstract":"It is shown that body doping can be used to match the Bulk FinFETs' DC performance with that of SOI FinFETs, even down to 22 nm technology node, by using calibrated full 3D device simulations. However higher body doping does not necessarily mean better performance always as there is a optimum body doping. The optimum doping should be carefully chosen such that device exhibits no punch through and no BTBT leakage currents. Thus careful body doping optimization is critical for the reliable device operation of novel Bulk FinFET structures.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131965092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of Negative Bias Temperature Instability in HfSiO(N)/TaN and SiO(N)/poly-Si pMOSFETs","authors":"V. Maheta, S. Purawat, G. Gupta","doi":"10.1109/IPFA.2007.4378064","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378064","url":null,"abstract":"In contrast to previous studies, the VT degradation during NBTI stress demonstrates power law time dependence as predicted by the R-D model as well as Arrhenius T activation for different nitrided/non-nitrided HfSiO(N)/TaN and SiO(N)/poly-Si devices. It is shown that measurement delay causes an increase in n. Different higher values of n reported earlier are artifacts of measurement delay. All splits of devices follow NBTI scaling scheme, EA,NBTI=n*EA,Diffusion regardless of the different gate stack materials. The difference in EADiffusion and EA,NBTI between HfSiO(N)/TaN and SiO(N)/poly-Si devices is attributed to different diffusion medium for hydrogen. Identical mechanism (primarily DeltaNIT driven) for VT degradation at longer stress time can be predicted for nitrided/non-nitrided HfSiO(N)/TaN and SiO(N)/poly-Si devices.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analytic model for the post-breakdown current in HfO2/TaN/TiN gate stacks","authors":"E. Miranda, K. Pey, R. Ranjan, C. Tung","doi":"10.1109/IPFA.2007.4378104","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378104","url":null,"abstract":"We have examined the post-BD currents in high-k/metal gate MOSFETs with the Si substrate under depletion and accumulation conditions. The experimental results seem to point out that the electronic properties of the substrate region close to the entrance of the BD spot play a central role in the description of the phenomenon. We have also examined the behavior of the post-BD current in terms of the normalized differential conductance. An approximated analytic expression has been provided.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"C-32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126487103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Karmarkar, X. Xu, S. Saha, X. Lin, G. Rollins, X. Lin
{"title":"A Compact Model Analysis of Layout Variation Impact on Mechanical Stress in Dielectrics","authors":"A. Karmarkar, X. Xu, S. Saha, X. Lin, G. Rollins, X. Lin","doi":"10.1109/IPFA.2007.4378060","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378060","url":null,"abstract":"The current industry trends towards reducing feature size and increasing integration density call for the use of copper (Cu) metallization and low permittivity (low-k) interlayer dielectrics (ILD). Low-k dielectrics are typically characterized by low mechanical strength, low hardness and high porosity (Blaine et al., 2002). The thermal mismatch stresses induced by the manufacturing process pose significant reliability challenges for the integration of Cu/Low-k interconnects because of the poorer mechanical characteristics of the low- k dielectrics (Cherault et al., 2005). Moreover, the geometry and the pattern of the metal lines have a significant impact on the thermomechanical stresses in multilevel interconnect structures, which in turn affect the interconnect reliability (Shen, 1999 and Yao et al., 2004). Interconnect processing, layout geometry and layout proximity effects can create regions of high stress concentrations and/or gradients in the interconnect structures employed in deep sub-micron technologies. These stress hot- spots are responsible for cracking and formation of voids in metal lines and the surrounding dielectric, thereby decreasing the overall yield (ogawa et al., 2002 and Lee et al., 2002). This paper presents a numerical analysis-based compact model approach to improve the manufacturability and reliability (design for manufacturing) of back-end-of-the-line (BEOL) structures, with emphasis on the dielectric reliability.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129298668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Failure Analysis on Low Pull Strength of Thermo-sonic Wedge Bond between Gold Wire and Gold Substrate of MEMS Device","authors":"S. K. Thakur, Gan Tai Kwee","doi":"10.1109/IPFA.2007.4378106","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378106","url":null,"abstract":"The damaged wire on the wedge resulted in physically thinning of the wire and caused low pull of second bond between gold wire and gold substrate of MEMS component. The thinned wire due to lower cross-section was unable to take high pull force and hence showed poor load sharing with the substrate and hence failed with low pull strength.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116005801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Shen, Liang-Feng Wen, T. Chuang, Y.-L. Chang, Shi-Chen Lin, Chen-May Huang, J.H. Chou
{"title":"Combine Micro-probing and ORBICH to Catch Non-recognizable Fault in RF and Mixed-Mode Integrated Circuits","authors":"C. Shen, Liang-Feng Wen, T. Chuang, Y.-L. Chang, Shi-Chen Lin, Chen-May Huang, J.H. Chou","doi":"10.1109/IPFA.2007.4378087","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378087","url":null,"abstract":"Fhis paper is to present a novel methodology to overcome above hardness, and two case study are brought out to demonstrate the application. In our methodology, no any new instrument was needed but only through these already accomplished EFA/PFA equipments. The key consideration to develop such ideas were due to keeping testability and effectiveness in these conventional tools for focusing on the capabilities of a foundry's available production.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123479271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ferrigno, P. Perdu, K. Sanchez, D. Lewis, M. Valletc, S. Dudit
{"title":"IC Debug and Defect Localization using Dynamic Laser Stimulation and Time-Resolved Emission","authors":"J. Ferrigno, P. Perdu, K. Sanchez, D. Lewis, M. Valletc, S. Dudit","doi":"10.1109/IPFA.2007.4378090","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378090","url":null,"abstract":"Dynamic optical techniques (light emission and laser stimulation techniques) are routinely used for precise IC defect localization. As device technology is more and more shrinking, developing new techniques for defect localization is becoming a crucial challenge. Dynamic Laser Stimulation (DLS) techniques based on near-infrared laser scanning are used for failure analysis, design debug and time margin studies or critical path analysis. Using Time Resolved Emission (TRE) technique, scan chain, timing and logic failure are shown to be quickly and precisely identified [1]. On 180nm and 120 nm test structures devices, we will present results showing the accuracy and the complementary of DLS and TRE in order to help Failure Analysists or Debug engineers to localize defect without performing physical analysis.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122127847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Po-Ying Chen, Shen-Li Chen, M. Tsai, M.H. Jing, T. Lin, Cheng-Chia Kuo
{"title":"The Defects of Silicon Reacted with Carbon Content Vapour in ULSI Nano-meter-Generation Technology","authors":"Po-Ying Chen, Shen-Li Chen, M. Tsai, M.H. Jing, T. Lin, Cheng-Chia Kuo","doi":"10.1109/IPFA.2007.4378101","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378101","url":null,"abstract":"This investigation considers in detail a defect called \"silicon substrate damaged defects\" and also introduces these defects' forming mechanisms and their root causes. These defects are likely to become increasing important in the future of deep-sub micrometer ULSI's situation. Two conditions typically result in silicon damaged defects during manufacturing processes namely: (1) watermark with carbon content and (2) the electrical charges accumulated on the silicon wafer surface.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}