The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

Abstract

The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.