{"title":"摩尔定律:CMOS缩放视角","authors":"S. Tyagi","doi":"10.1109/IPFA.2007.4378049","DOIUrl":null,"url":null,"abstract":"In this paper we presented a retrospective on Moore's law, highlighting the salient feature of industry leading 65nm CMOS technology for high performance logic, and highlighted future challenges and approaches to overcome those.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"461 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Moore's Law: A CMOS Scaling Perspective\",\"authors\":\"S. Tyagi\",\"doi\":\"10.1109/IPFA.2007.4378049\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we presented a retrospective on Moore's law, highlighting the salient feature of industry leading 65nm CMOS technology for high performance logic, and highlighted future challenges and approaches to overcome those.\",\"PeriodicalId\":334987,\"journal\":{\"name\":\"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"461 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2007.4378049\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2007.4378049","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we presented a retrospective on Moore's law, highlighting the salient feature of industry leading 65nm CMOS technology for high performance logic, and highlighted future challenges and approaches to overcome those.