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2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Failure Mechanisms of AIN based RF-MEMS Switches Under DC and ESD Stresses 基于AIN的RF-MEMS开关在直流和ESD应力下的失效机理
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378070
J. Ruan, N. Nolhier, M. Bafleur, L. Bary, N. Mauran, F. Coccetti, T. Lisec, R. Plana
{"title":"Failure Mechanisms of AIN based RF-MEMS Switches Under DC and ESD Stresses","authors":"J. Ruan, N. Nolhier, M. Bafleur, L. Bary, N. Mauran, F. Coccetti, T. Lisec, R. Plana","doi":"10.1109/IPFA.2007.4378070","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378070","url":null,"abstract":"Today, we report only one paper concerning this issue and we believe that it deserves to go deeper in detail concerning the physic of failure related to ESD stresses. The second part of this paper is devoted to the reliability investigation of AIN-based capacitive switches under ESD stresses.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"42 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123659975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of CoWP Capping Layers on Dielectric Breakdown of SiO2 cop盖层对SiO2介电击穿的影响
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378058
J. Gambino, Fen Chen, S. Mongeon, D. Meatyard, T. Lee, B. Lee, H. Bamnolker, L. Hall, N. Li, M. Hernández, P. Little, M. Hamed, I. Ivanov
{"title":"Effect of CoWP Capping Layers on Dielectric Breakdown of SiO2","authors":"J. Gambino, Fen Chen, S. Mongeon, D. Meatyard, T. Lee, B. Lee, H. Bamnolker, L. Hall, N. Li, M. Hernández, P. Little, M. Hamed, I. Ivanov","doi":"10.1109/IPFA.2007.4378058","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378058","url":null,"abstract":"Leakage and dielectric breakdown of SiO2 are studied for Cu interconnect structures with either stand-alone CoWP or two-layer CoWP+SiN caps. Without a post-CoWP plasma clean, there are many early fails and the dielectric breakdown exhibits bimodal behavior. By adding a plasma clean after CoWP deposition, the early fails can be eliminated and high dielectric breakdown is achieved. The improvement in dielectric breakdown with the plasma clean is greater for the two-layer cap compared to the stand-alone cap, probably due to the extra plasma clean associated with SiN deposition.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133838181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliability Analysis of Torsional Varactor 扭转变矩器可靠性分析
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378069
C. Venkatesh, N. Bhat
{"title":"Reliability Analysis of Torsional Varactor","authors":"C. Venkatesh, N. Bhat","doi":"10.1109/IPFA.2007.4378069","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378069","url":null,"abstract":"A torsional MEMS varactor with wide dynamic range, lower actuation voltage and isolation between actuation voltage and signal voltage has been proposed in C. Venkatesh et al. (2005). In this paper we address the effects of pull-in, residual stress and continuous cycling on the performance of torsional MEMS varactor.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"8 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of Technological Parameters on the Behavior during Aging at High Temperature of Various Packages, in the Automotive Environment 工艺参数对汽车环境下各种封装高温老化性能的影响
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378062
B. M. Auguste, L. Pascal, G. Annabelle, F. Hélène
{"title":"Influence of Technological Parameters on the Behavior during Aging at High Temperature of Various Packages, in the Automotive Environment","authors":"B. M. Auguste, L. Pascal, G. Annabelle, F. Hélène","doi":"10.1109/IPFA.2007.4378062","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378062","url":null,"abstract":"The failure mechanism related to Kirkendall voids is a consequence of the intermetallic thickness growth (Au- Al). It impacts the wires bonding reliability at high temperature. Temperature accelerates the intermetallic thickness growth as the diffusion between gold and aluminium is accelerated. Moreover, the role of the package geometry was identified, and experimental results were confirmed by both simple analytical model and FEM simulations. This study confirms a good choice for the automotive environment at high thermal aging (150degC). Finally, the WP and BS tests of the thermal behavior do not allow a continuous monitoring of the degradation, and are time and sample consuming. So we are developing a measurement procedure coupled to a theoretical study of the resistance variation of the wire bond, aimed to produce an early failure indicator of the ball bonds.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132873544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Degradation- and Failure Mode Analysis of III-V Nitride Devices III-V型氮化物器件的退化与失效模式分析
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378102
J. Tharian
{"title":"Degradation- and Failure Mode Analysis of III-V Nitride Devices","authors":"J. Tharian","doi":"10.1109/IPFA.2007.4378102","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378102","url":null,"abstract":"In this work, different failure modes and degradation mechanisms of AlInGaN LEDs were studied under different stress conditions. Another aim of this work was to develop a classification criteria of the LEDs based on initial RBL characteristics and enable the manufacturers ensure better reliability standards.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Transient-Induced Latchup in CMOS Integrated Circuits due to Electrical Fast Transient (EFT) Test 由电快速瞬变(EFT)测试引起的CMOS集成电路瞬态感应锁存
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378095
Cheng-Cheng Yen, M. Ker
{"title":"Transient-Induced Latchup in CMOS Integrated Circuits due to Electrical Fast Transient (EFT) Test","authors":"Cheng-Cheng Yen, M. Ker","doi":"10.1109/IPFA.2007.4378095","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378095","url":null,"abstract":"The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-mum CMOS technology.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114393690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Soft Defects: Challenge and Chance for Failure Analysis 软缺陷:失效分析的挑战与机遇
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378091
C. Burmer, C. Brillert, Zhongling Qian
{"title":"Soft Defects: Challenge and Chance for Failure Analysis","authors":"C. Burmer, C. Brillert, Zhongling Qian","doi":"10.1109/IPFA.2007.4378091","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378091","url":null,"abstract":"Failure analysis on advanced logic and mixed signal ICs more and more has to deal with so called 'soft defects'. In this paper, an analysis flow especially for parameter dependent scan fails is presented. For the two major localization techniques, namely soft defect localization (SDL) and internal signal measurement enhanced activation and localization procedures using test systems are proposed.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125269824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Development and Characterization of Silicon via Tapering Process for 3D System in Packaging Application 应用于封装3D系统的渐缩工艺硅的开发与表征
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378105
N. Ranganathan, L. Ebin, N. Balasubramanian, K. Prasad, K. Pey
{"title":"Development and Characterization of Silicon via Tapering Process for 3D System in Packaging Application","authors":"N. Ranganathan, L. Ebin, N. Balasubramanian, K. Prasad, K. Pey","doi":"10.1109/IPFA.2007.4378105","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378105","url":null,"abstract":"Through-silicon interconnection technology is considered to be a critical and enabling technology for 3-D stacking of electronic and electro-mechanical systems, which is believed to be a solution to the performance bottleneck associated with traditional and inherently long 2-D chip-to-chip interconnections. An obvious advantage in this architecture is that it leads to space saving for portable and hand-held applications. It also offers significant performance improvement for high frequency applications as the interconnection lengths and associated parasitics are reduced [1, 2]. The development of 3-D integration technologies is further motivated by shorter chip-to-chip interconnection lengths and reduced parasitics associated with wire-bonded packages for high frequency application. Hence, it is crucial to have a reliable and manufacturable through-silicon interconnect technology.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"369 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124624959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Trends in memory technology - reliability perspectives, challenges and opportunities 存储器技术的发展趋势——可靠性的前景、挑战和机遇
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378072
C. Mouli, K. Prall, C. Roberts
{"title":"Trends in memory technology - reliability perspectives, challenges and opportunities","authors":"C. Mouli, K. Prall, C. Roberts","doi":"10.1109/IPFA.2007.4378072","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378072","url":null,"abstract":"As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics. Some of the challenges are common between these technologies while some are unique. New materials and cell structures are being introduced to address some of these issues and provide further scaling opportunities.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121032799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reliability Assessment on Highly Manufacturable MOSFETs with Metal Gate and Hf based Gate Dielectrics 金属栅极和Hf基栅极电介质高可制造mosfet的可靠性评估
2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI: 10.1109/IPFA.2007.4378051
R. Choi, C. Young, C. Kang, D. Heh, G. Bersuker, S. Krishnan, R. Kirsch, A. Neugroschel, S.C. Song, B. Lee, R. Jammy
{"title":"Reliability Assessment on Highly Manufacturable MOSFETs with Metal Gate and Hf based Gate Dielectrics","authors":"R. Choi, C. Young, C. Kang, D. Heh, G. Bersuker, S. Krishnan, R. Kirsch, A. Neugroschel, S.C. Song, B. Lee, R. Jammy","doi":"10.1109/IPFA.2007.4378051","DOIUrl":"https://doi.org/10.1109/IPFA.2007.4378051","url":null,"abstract":"After over 10 years of intensive study on high-k dielectric and metal gate electrode to replace silicon based materials (Si02 or SiON gate dielectric and polysilicon gate) in the complementary-metal-oxide-semiconductor (CMOS) application, it was claimed that hafnium based dielectric and metal gate are finally ready to be implemented in 45nm technology and beyond. It was reported that the minority carrier mobility in the metal-oxide-semiconductor field effect transistor (MOSFET) with hafnium oxide (Hf02) was improved significantly and performance reaches the comparable level of that of MOSFETs with silicon oxynitride even with further scaled equivalent oxide thickness (EOT). Since the device performance has been optimized, the focus of the high-k dielectric study shifts toward the device reliability issues.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125978824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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