由电快速瞬变(EFT)测试引起的CMOS集成电路瞬态感应锁存

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI:10.1109/IPFA.2007.4378095

Cheng-Cheng Yen, M. Ker

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引用次数: 4

摘要

通过实验验证，研究了电快速瞬变(EFT)测试中CMOS集成电路的瞬态感应闭锁(TLU)问题。在EFT测试下，利用正、负电压脉冲，可以在寄生pnpn结构的CMOS集成电路中触发TLU。提出了CMOS集成电路中TLU的物理机制，并在时域上进行了实验验证。用0.18 μ m CMOS工艺制作的可控硅(SCR)测试结构验证了所有的实验结果。

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Transient-Induced Latchup in CMOS Integrated Circuits due to Electrical Fast Transient (EFT) Test

The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-mum CMOS technology.

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2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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