Development and Characterization of Silicon via Tapering Process for 3D System in Packaging Application

Abstract

Through-silicon interconnection technology is considered to be a critical and enabling technology for 3-D stacking of electronic and electro-mechanical systems, which is believed to be a solution to the performance bottleneck associated with traditional and inherently long 2-D chip-to-chip interconnections. An obvious advantage in this architecture is that it leads to space saving for portable and hand-held applications. It also offers significant performance improvement for high frequency applications as the interconnection lengths and associated parasitics are reduced [1, 2]. The development of 3-D integration technologies is further motivated by shorter chip-to-chip interconnection lengths and reduced parasitics associated with wire-bonded packages for high frequency application. Hence, it is crucial to have a reliable and manufacturable through-silicon interconnect technology.