阻挡层TaN结合Al衬垫结构在Cu工艺中的失效模式研究

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2007-07-11 DOI:10.1109/IPFA.2007.4378097

Po-Ying Chen, Shen-Li Chen, M. Tsai, M.H. Jing, T. Lin

{"title":"阻挡层TaN结合Al衬垫结构在Cu工艺中的失效模式研究","authors":"Po-Ying Chen, Shen-Li Chen, M. Tsai, M.H. Jing, T. Lin","doi":"10.1109/IPFA.2007.4378097","DOIUrl":null,"url":null,"abstract":"CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called \"cosmetic defects\" in 130- and 90-nm complementary metal-oxide-semiconductor (CMOS) process node.","PeriodicalId":334987,"journal":{"name":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The Failure Mode Investigation of Barrier Layer TaN Combined with Al Pad Architecture using in Cu Process\",\"authors\":\"Po-Ying Chen, Shen-Li Chen, M. Tsai, M.H. Jing, T. Lin\",\"doi\":\"10.1109/IPFA.2007.4378097\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called \\\"cosmetic defects\\\" in 130- and 90-nm complementary metal-oxide-semiconductor (CMOS) process node.\",\"PeriodicalId\":334987,\"journal\":{\"name\":\"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2007.4378097\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2007.4378097","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

CMOS芯片的几何尺寸越来越小，其互连对芯片整体性能的影响也越来越大。本文提出了一种集成制程的良率提升策略，以克服130 nm和90 nm互补金属氧化物半导体(CMOS)制程节点中所谓的“表面缺陷”。

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The Failure Mode Investigation of Barrier Layer TaN Combined with Al Pad Architecture using in Cu Process

CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called "cosmetic defects" in 130- and 90-nm complementary metal-oxide-semiconductor (CMOS) process node.

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2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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