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Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.最新文献

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Characterization and modeling of high frequency monolithic PIN diodes on SOI substrate SOI基板上高频单片PIN二极管的特性与建模
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398216
E. Duraz, L. Duvillaret, P. Ferrari, J. Coutaz, J. Ghesquiers, É. Estebe
{"title":"Characterization and modeling of high frequency monolithic PIN diodes on SOI substrate","authors":"E. Duraz, L. Duvillaret, P. Ferrari, J. Coutaz, J. Ghesquiers, É. Estebe","doi":"10.1109/SMIC.2004.1398216","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398216","url":null,"abstract":"We present high frequency measurements, simulation and modeling of PIN diodes on SOI substrate from 40 MHz to 40 GHz and from 74 to 114 GHz. Comparison between simulations and measurements brings to the fore a frequency dependent PIN diode capacitance with reverse bias. We show that the free carriers injected in the diode intrinsic channel induce a frequency dependent complex permittivity of the silicon substrate that is responsible for the frequency behaviour of the PIN diode capacitance. Moreover, no adjustable parameter is required in this model as all the required parameters can be easily measured.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130956269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SOI voltage controlled ring oscillator SOI压控环形振荡器
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398208
S. Venkataraman, X. Zhu, Y. Zhang, C. Hutchens
{"title":"SOI voltage controlled ring oscillator","authors":"S. Venkataraman, X. Zhu, Y. Zhang, C. Hutchens","doi":"10.1109/SMIC.2004.1398208","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398208","url":null,"abstract":"Seven-stage and twenty-one-stage voltage controlled inverter-chain ring oscillators are fabricated in SOI 0.5 /spl mu/m technology. It is found that the oscillation is very robust to the variation of power supply voltage, and there is no significant change of timing jitter. When the body voltages of the MOSFETs are swept, the oscillation frequency has a linear dependence.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133035399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synthesized high-impedance CMOS thin-film transmission line 合成高阻抗CMOS薄膜传输线
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398229
Hsien-Hung Wu, Hsien-Shun Wu, Ching-Kuang C. Tzuang
{"title":"Synthesized high-impedance CMOS thin-film transmission line","authors":"Hsien-Hung Wu, Hsien-Shun Wu, Ching-Kuang C. Tzuang","doi":"10.1109/SMIC.2004.1398229","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398229","url":null,"abstract":"A synthetic quasi-TEM CMOS transmission line (TL) of wide range characteristic impedance from 58.3 to 95 /spl Omega/ is presented for miniaturization of CMOS RFIC. The synthetic TL consists of unit cells made of complementary-conducting strips (CCS) and connecting arm for signal interface residing on the M5 and M1 metal layers of a typical 0.25 /spl mu/m 1P5M CMOS process. Measured results and theoretical data indicate that the loss per guiding wavelength of the meandered CCS TL is about 13% lower than that of the meandered microstrip of characteristic impedance 86.4 /spl Omega/ at 40 GHz.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122228479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Speed and power performance comparison of state-of-the-art CMOS and SiGe RF transistors 最先进的CMOS和SiGe射频晶体管的速度和功率性能比较
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398181
B. Jagannathan, D. Greenberg, D. Sanderson, J. Rieh, J. Pekarik, J. Plouchart, G. Freeman
{"title":"Speed and power performance comparison of state-of-the-art CMOS and SiGe RF transistors","authors":"B. Jagannathan, D. Greenberg, D. Sanderson, J. Rieh, J. Pekarik, J. Plouchart, G. Freeman","doi":"10.1109/SMIC.2004.1398181","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398181","url":null,"abstract":"DC and RF characteristics of Si nFETs and SiGe HBTs are compared in IBM's leading-edge production RFCMOS and BiCMOS technologies at 90 and 130 nm nodes respectively. Underlying performance trade-offs to achieve low power circuit operation are investigated.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116917131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
CMOS LNA design for system-on-chip receiver stages 片上系统接收机级的CMOS LNA设计
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398195
Ali Tell, Murat Askar
{"title":"CMOS LNA design for system-on-chip receiver stages","authors":"Ali Tell, Murat Askar","doi":"10.1109/SMIC.2004.1398195","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398195","url":null,"abstract":"Narrowband single-ended inductive source degenerated low noise amplifiers (LNAs) for \"system-on-chip\" receiver stages have been designed, simulated and compared using the Mietec CMOS 0.7 /spl mu/m process and the Cadence/BSIM3v3 tool with active or L-biased DC-bias circuitries. Since there is an intention to use LNAs for GSM and S-band low earth orbit (LEO) space applications, the operating frequencies have been chosen as 900 MHz, 2025 MHz and 2210 MHz.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122206278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.575 GHz BiCMOS GPS low noise amplifier for low power application 低功耗应用的1.575 GHz BiCMOS GPS低噪声放大器
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398197
A. Agarwal, G. S. Chandel, A. Biswas
{"title":"A 1.575 GHz BiCMOS GPS low noise amplifier for low power application","authors":"A. Agarwal, G. S. Chandel, A. Biswas","doi":"10.1109/SMIC.2004.1398197","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398197","url":null,"abstract":"An integrated circuit representation of an LNA at 1.575 GHz using BiCMOS has been developed for low power applications. A single stage architecture, in conjunction with a tank circuit, is used to optimize the gain and noise performance simultaneously, with a power supply of 3.3 V and current rating of 4 mA. The LNA circuit has been designed with a noise figure of 1.5 dB and gain around 25 dB. To achieve high gain even with low power consumption, the tank circuit has been used and this affects the performance of the circuit in terms of a low third order intercept of the order of -46 dBm.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116659278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Monolithically integrated IMPATT diodes for Ka-band transmitters 用于ka波段发射机的单片集成IMPATT二极管
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398204
C. Schollhorn, H. Xu, M. Morschbach, E. Kasper
{"title":"Monolithically integrated IMPATT diodes for Ka-band transmitters","authors":"C. Schollhorn, H. Xu, M. Morschbach, E. Kasper","doi":"10.1109/SMIC.2004.1398204","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398204","url":null,"abstract":"Emanating from S-parameter measurements on monolithically integrated IMPATT diodes in the Ka-band a completely integrated transmitter is designed and simulated. The resonator is built with coplanar waveguides. A planar slot antenna is used for the emission of the RF signal. To improve the performance of the antenna the silicon substrate has to be thinned to a thickness of 200 /spl mu/m.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"613 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124693062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RF small signal modeling of tri-gate /spl Omega/ MOSFETs implemented on bulk Si wafers 在块状硅晶片上实现的三栅极/spl ω / mosfet射频小信号建模
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398220
Nam-Kyun Tak, Jong-Ho Lee
{"title":"RF small signal modeling of tri-gate /spl Omega/ MOSFETs implemented on bulk Si wafers","authors":"Nam-Kyun Tak, Jong-Ho Lee","doi":"10.1109/SMIC.2004.1398220","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398220","url":null,"abstract":"The RF characteristics of the tri-gate /spl Omega/ MOSFETs were studied firstly by using 3-dimensional device simulator. Small signal model parameters were extracted using an equivalent circuit and compared with those of a planar MOSFET. The /spl Omega/ MOSFET shows lower sensitivity of g/sub mb/ and V/sub T/ with substrate bias than the planar device. The tri-gale /spl Omega/ MOSFETs shows a higher cut-off frequency at a lower drain current.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123243788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SiGe BiCMOS LNA meeting FCC Part 15 ultra-wideband restrictions SiGe BiCMOS LNA满足FCC第15部分超宽带限制
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398198
Y.J. Llano, A.H. Guardado
{"title":"SiGe BiCMOS LNA meeting FCC Part 15 ultra-wideband restrictions","authors":"Y.J. Llano, A.H. Guardado","doi":"10.1109/SMIC.2004.1398198","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398198","url":null,"abstract":"A fully integrated SiGe BiCMOS low noise amplifier (LNA) for ultra-wideband (UWB) has been implemented in a 0.4 /spl mu/m SiGe BiCMOS technology from Motorola Semiconductors. It features a cut-off frequency of 46 GHz. The LNA exhibits a wide bandwidth, from 3 to 10.5 GHz, with a flat gain of 24 dB. This amplifier shows a noise figure below 4.4 dB over the whole bandwidth and achieves good return losses without any matching network. This 3-10.5 GHz SiGe LNA design meets FCC Part 15 restrictions for UWB technology.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131000538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Wafer-level three-dimensional monolithic integration for heterogeneous silicon ICs 异质硅集成电路的晶圆级三维单片集成
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI: 10.1109/SMIC.2004.1398163
R. Gutmann, J. Lu, S. Devarajan, A. Zeng, K. Rose
{"title":"Wafer-level three-dimensional monolithic integration for heterogeneous silicon ICs","authors":"R. Gutmann, J. Lu, S. Devarajan, A. Zeng, K. Rose","doi":"10.1109/SMIC.2004.1398163","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398163","url":null,"abstract":"A 3D IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer vias and compatibility of the process steps with 130 nm CMOS SOI devices and circuits indicate the viability of the process flow. Memory-intensive digital processors with large L2 caches have shorter access time and cycle time with 3D implementations. Performance advantages of recently designed SiGe BiCMOS pipelined A/D converters have promising figure-of-merits and illustrate partitioning issues for silicon RF ICs. Comparison with system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123085357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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