{"title":"Efficient encoding scheme for ultra-fast flash ADC","authors":"J. Choudhury, G. Massiha","doi":"10.1109/SMIC.2004.1398226","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398226","url":null,"abstract":"We propose an efficient encoding scheme to be designed using the robust principle of programmable logic arrays (PLA) for an ultra-fast flash analog to digital converter (ADC). High-speed operation in the MHz-GHz range is the major goal of flash ADC design. A high-speed ADC needs a fast comparator, a high-speed encoder, and a fast sample and hold (S-H) circuit. These three areas of high-speed ADC design require equally careful attention. Technological advancement has produced superior high-speed comparators. The speed of encoders has been dealt with mostly on the algorithmic part. We propose a CMOS based encoder design to be integrated with a CMOS based high-speed comparator for system-on-chip (SoC). Depending on the availability of high-speed comparators, our design exploits the design of the comparator for the benefit of speeding up the encoder.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115929513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Substrate coupling noise issues in silicon technology","authors":"K. Jenkins","doi":"10.1109/SMIC.2004.1398175","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398175","url":null,"abstract":"Several factors are combining to increase concern about substrate coupling noise, or crosstalk, in silicon integrated circuits: there is a growing use of analog and mixed signal circuits in semiconductor products, there is greater integration density, and circuit frequencies are steadily increasing. Although the basic principles of electrical signal conduction through a semiconducting substrate are well understood, there is still a relatively poor understanding of the practical aspects of substrate-coupled noise: how important is substrate crosstalk in real applications? How good are the design guidelines for reducing crosstalk, or are accurate substrate modeling and simulation tools a necessity? What technology features can be used to reduce the coupling? This paper reviews progress in answering these questions.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127192343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Gaucher, T. Beukema, S. Reynolds, B. Floyd, T. Zwick, U. Pfeiffer, D. Liu, J. Cressler
{"title":"MM-wave transceivers using SiGe HBT technology","authors":"B. Gaucher, T. Beukema, S. Reynolds, B. Floyd, T. Zwick, U. Pfeiffer, D. Liu, J. Cressler","doi":"10.1109/SMIC.2004.1398172","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398172","url":null,"abstract":"High-speed wireless technology has been evolving with roughly 2/spl times/ speed improvements every 18 months. Currently the wireless local-area network (WLAN) and wireless personal-area network (WPAN) spaces are developing new standards to increase wireless speeds beyond the 10-54 Mbit/s achieved in the first and second generation IEEE wireless network standards. Challenging issues which must be addressed in these new high-rate standards include FCC restrictions on maximum radiated power and power spectral density, bandwidth limitations in the available 2.4 and 5 GHz ISM bands, and cost and power required to support the high date rates in portable devices. This paper discusses the realization of a mm-wave transceiver in advanced SiGe HBT technology for application in high-speed mm-wave wireless systems. A low-power, integrated 60 GHz transceiver opens up the potential for economical high-speed wireless systems which can take advantage of >5 GHz of unlicensed spectrum available in the 60 GHz ISM band.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116211203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Yoshihara, H. Sugawara, H. Ito, K. Okada, K. Masu
{"title":"A wide tuning range CMOS VCO using variable inductor","authors":"Y. Yoshihara, H. Sugawara, H. Ito, K. Okada, K. Masu","doi":"10.1109/SMIC.2004.1398223","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398223","url":null,"abstract":"The paper presents a novel wide tuning range CMOS VCO using an on-chip variable inductor as an additional variable element to extend tuning range. The VCO was fabricated using standard 0.35 /spl mu/m CMOS process with three metal layers, and could be tuned widely from 2.13 GHz to 3.28 GHz without degradation of phase noise.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122779369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-Q integrated passive elements for high frequency applications","authors":"Dimitris Peroulis, S. Mohammadi, L. Katehi","doi":"10.1109/SMIC.2004.1398158","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398158","url":null,"abstract":"Using MEMS fabrication technology, we have demonstrated very high frequency and high quality factor (Q) varactors, inductors and transformers on a Si substrate. On high resistivity Si, this technology results in broadband analog varactors with continuous tuning range as high as 3:1 and 1 nH inductors with Q>60 at frequencies of 3 to 7 GHz. High efficiency high-Q transformers with coupling factors 0.6<k<0.9 are achieved with very high self-resonance frequencies (8 GHz<f/sub res/<16 GHz). This technology is compatible with Si fabrication technologies and can be either implemented as a post-processing step or as a part of a vertical chip to interposer packaging scheme.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131093704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1-V 5 GHz low phase noise LC-VCO using voltage-dividing and bias-level shifting technique","authors":"Taeksang Song, E. Yoon","doi":"10.1109/SMIC.2004.1398174","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398174","url":null,"abstract":"In this paper, we present a 1 V 5.2 GHz VCO using voltage-dividing and bias-level shifting technique to prevent loaded Q-factor degradation and increase oscillation amplitude. The proposed VCO achieves a phase noise of 115.5 dBc/Hz at 1 MHz offset from a 5.2 GHz carrier frequency with 3 mA bias current from 1.0 V power supply. Tuning range is 450 MHz by changing the control bias from 0 V to 1.0 V.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124605816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of scalable models for patterned-ground-shield inductors in SiGe BiCMOS technology","authors":"R. Svitek, A. S. Klein, M. Clifford, S. Raman","doi":"10.1109/SMIC.2004.1398205","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398205","url":null,"abstract":"This paper presents the characterization and modeling of a group of monolithic spiral inductors with various patterned ground shield structures fabricated in a 0.18 /spl mu/m SiGe:C RFBiCMOS process. A direct comparison of two different types of ground shields, center-grounded (CGS) and perimeter-grounded (PGS), each fabricated in two different conductor levels, polysilicon and metal-one, is made. Fabricated inductors are characterized using on-wafer measurement with de-embedding of pad parasitics. A 36% improvement in the inductor quality factor over the unshielded inductor is realized using the CGS in polysilicon and metal-one, and using the PGS in polysilicon. Finally, a scalable lumped-element model that accounts for the effects of the different ground shield structures is proposed, and preliminary results of model extraction are presented.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130210022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A statistical tool for probing the coupling between noisy traps in semiconductor devices, with application to 1/f noise in SiGe HBTs","authors":"J. Johansen, Y. Birkelund, Z. Jin, J. Cressler","doi":"10.1109/SMIC.2004.1398182","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398182","url":null,"abstract":"We have analyzed random telegraph signal noise in the base current of a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) from a commercial SiGe HBT technology. We use higher order statistics to test for non-linear coupling between frequency components in the noise signal. We have decomposed the time series into a multilevel random telegraph signal (RTS) and the remaining noise. The random telegraph signal is found to contribute with Lorentzian 1/f/sup 2/-shaped spectra. We show that the non-linear coupling found is directly connected to the random telegraph signal part of the noise.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128659576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel low power low voltage LNA and mixer for WLAN IEEE 802.11a standard","authors":"Xuezhen Wang, R. Weber","doi":"10.1109/SMIC.2004.1398210","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398210","url":null,"abstract":"The paper presents a 5.8 GHz low voltage low noise amplifier (LNA) and a down-conversion mixer design integrated in a TSMC 0.18 /spl mu/m CMOS process. The LNA has a cascode inductive source degeneration structure. The proposed mixer features an RF input stage that converts the RF input voltage to current, which is coupled to the core of a Gilbert cell using a current mirror. This implementation eliminates the current source transistor at the bottom and furthermore reduces the supply voltage. The LO frequency is at 5.6 GHz. The designed LNA and mixer require only a 1.5 V supply voltage and consumes 17.2 mW DC power. At 5.8 GHz, this front-end circuit has a single-sideband noise figure (SSB NF) of 7.8 dB, with input return loss of -8 dB, with output return loss of -14.5 dB, third-order input intercept point (IIP3) of -20.56 dBm, and conversion gain of 15.7 dB.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"149 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115584602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic characterization and model comparison of high frequency FET devices","authors":"M. Dawande","doi":"10.1109/SMIC.2004.1398201","DOIUrl":"https://doi.org/10.1109/SMIC.2004.1398201","url":null,"abstract":"A precision dynamic characterization, using fast pulses of varied amplitude with duration of 0.2 /spl mu/s, is performed on high frequency FET devices. The responsible parameters for large signal models are extracted and the models are developed for static and dynamic characteristics. The binning models for the Statz, TOM and Angelov models are developed in the ADS simulation tool and a comparative evaluation is presented.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130142439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}