Efficient encoding scheme for ultra-fast flash ADC

Abstract

We propose an efficient encoding scheme to be designed using the robust principle of programmable logic arrays (PLA) for an ultra-fast flash analog to digital converter (ADC). High-speed operation in the MHz-GHz range is the major goal of flash ADC design. A high-speed ADC needs a fast comparator, a high-speed encoder, and a fast sample and hold (S-H) circuit. These three areas of high-speed ADC design require equally careful attention. Technological advancement has produced superior high-speed comparators. The speed of encoders has been dealt with mostly on the algorithmic part. We propose a CMOS based encoder design to be integrated with a CMOS based high-speed comparator for system-on-chip (SoC). Depending on the availability of high-speed comparators, our design exploits the design of the comparator for the benefit of speeding up the encoder.