合成高阻抗CMOS薄膜传输线

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI:10.1109/SMIC.2004.1398229

Hsien-Hung Wu, Hsien-Shun Wu, Ching-Kuang C. Tzuang

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引用次数: 8

摘要

为实现CMOS RFIC的小型化，提出了58.3 ~ 95 /spl ω /宽范围特性阻抗的合成准tem CMOS传输线(TL)。合成TL由互补导电带(CCS)和信号接口连接臂组成，位于典型的0.25 /spl μ m 1P5M CMOS工艺的M5和M1金属层上。实测结果和理论数据表明，在40 GHz时，弯曲CCS TL的每导波损耗比特征阻抗为86.4 /spl ω /的弯曲微带低13%左右。

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Synthesized high-impedance CMOS thin-film transmission line

A synthetic quasi-TEM CMOS transmission line (TL) of wide range characteristic impedance from 58.3 to 95 /spl Omega/ is presented for miniaturization of CMOS RFIC. The synthetic TL consists of unit cells made of complementary-conducting strips (CCS) and connecting arm for signal interface residing on the M5 and M1 metal layers of a typical 0.25 /spl mu/m 1P5M CMOS process. Measured results and theoretical data indicate that the loss per guiding wavelength of the meandered CCS TL is about 13% lower than that of the meandered microstrip of characteristic impedance 86.4 /spl Omega/ at 40 GHz.

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Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.

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