Wafer-level three-dimensional monolithic integration for heterogeneous silicon ICs

Abstract

A 3D IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer vias and compatibility of the process steps with 130 nm CMOS SOI devices and circuits indicate the viability of the process flow. Memory-intensive digital processors with large L2 caches have shorter access time and cycle time with 3D implementations. Performance advantages of recently designed SiGe BiCMOS pipelined A/D converters have promising figure-of-merits and illustrate partitioning issues for silicon RF ICs. Comparison with system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.