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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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High performance pMOSFETs with Ni(Si/sub x/Ge/sub 1-x/)/poly-Si/sub 0.8/Ge/sub 0.2/ gate 具有Ni(Si/sub x/Ge/sub 1-x/)/多晶硅/sub 0.8/Ge/sub 0.2栅极的高性能pmosfet
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852791
J. Ku, C.-J. Choi, S. Song, S. Choi, K. Fujihara, H. Kang, S.I. Lee, H.-G. Choi, D. Ko
{"title":"High performance pMOSFETs with Ni(Si/sub x/Ge/sub 1-x/)/poly-Si/sub 0.8/Ge/sub 0.2/ gate","authors":"J. Ku, C.-J. Choi, S. Song, S. Choi, K. Fujihara, H. Kang, S.I. Lee, H.-G. Choi, D. Ko","doi":"10.1109/VLSIT.2000.852791","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852791","url":null,"abstract":"For the first time, Ni salicide process is applied directly on poly-Si/sub 0.8/Ge/sub 0.2/ gate, and pMOSFETs utilizing Ni(Si/sub x/Ge/sub 1-x/)/poly-Si/sub 0.8/Ge/sub 0.2/ gate are fully characterized. The excellent value (/spl sim/5/spl Omega///spl square/) of sheet resistance is achieved from 0.15 /spl mu/m Ni(Si/sub x/Ge/sub 1-x/)/Si/sub 0.8/Ge/sub 0.2/ gate, while Co salicide process applied on Si/sub 0.8/Ge/sub 0.2/ gate results in R/sub s/ fail due to Ge segregation. It is also important to note that, with poly-Si/sub 0.8/Ge/sub 0.2/ gate and Ni salicide process, the current drivability of pMOSFETs is significantly improved due to less gate poly depletion and lower source-to-drain resistance (R/sub sd/). Conclusively, Ni salicide is the exclusive process for successful germanosilicide formation on poly-Si/sub 0.8/Ge/sub 0.2/ gate without poly-Si buffer layer and Ni(Si/sub x/Ge/sub 1-x/)/poly-Si/sub 0.8/Ge/sub 0.2/ gate can increase L/sub dsat/ of pMOSFETs by 20% as compared to conventional CoSi/sub 2//poly-Si gate structure.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131950757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS 良好控制，选择性下蚀刻的Si/SiGe栅极，用于射频和高性能CMOS
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852807
T. Skotnicki, M. Jurczak, J. Martins, M. Paoli, B. Tormen, R. Pantel, C. Hernandez, I. Campidelli, E. Josse, G. Ricci, J. Galvier
{"title":"Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS","authors":"T. Skotnicki, M. Jurczak, J. Martins, M. Paoli, B. Tormen, R. Pantel, C. Hernandez, I. Campidelli, E. Josse, G. Ricci, J. Galvier","doi":"10.1109/VLSIT.2000.852807","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852807","url":null,"abstract":"We propose a new process of selective lateral under-etching of bi-layered Si/SiGe gates, aimed at the formation of well-controlled notches. Weak Ge mole fraction (/spl les/30%) and moderate notch depth render the notch formation compatible with standard CMOS process, and prevent dispersions. The latter, in the case of a shallow notch (/spl les/25 nm) are even smaller than in reference Si-gate devices without a notch. Higher commutation speed, better transconductance and better SGE/DIBL immunity are demonstrated experimentally on notched gate devices.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134493030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Advantage of radical oxidation for improving reliability of ultra-thin gate oxide 自由基氧化提高超薄栅极氧化物可靠性的优势
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852815
Yuji Saito, K. Sekine, '. NaokiUeda, M. Hirayama, S. Sugawa, T. Ohmi
{"title":"Advantage of radical oxidation for improving reliability of ultra-thin gate oxide","authors":"Yuji Saito, K. Sekine, '. NaokiUeda, M. Hirayama, S. Sugawa, T. Ohmi","doi":"10.1109/VLSIT.2000.852815","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852815","url":null,"abstract":"This paper focuses attention on the advantage of oxygen radical oxidation by a microwave-excited high-density Kr/O/sub 2/ plasma for improving the disadvantages of conventional thermal oxidation processes using H/sub 2/O and/or O/sub 2/ molecules, and demonstrates that the Kr/O/sub 2/ plasma oxidation process can improve the thickness variation on shallow-trench isolation and integrity of silicon oxide not only on the [100] surface but also on the [111] surface compared to those of conventional thermal oxidation processes.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134180714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI 0.25 /spl mu/m使用模式化SOI合并批量DRAM和SOI逻辑
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852772
R. Hannon, S. Iyer, D. Sadana, J. Rice, H. Ho, B. Khan, S. Iyer
{"title":"0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI","authors":"R. Hannon, S. Iyer, D. Sadana, J. Rice, H. Ho, B. Khan, S. Iyer","doi":"10.1109/VLSIT.2000.852772","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852772","url":null,"abstract":"The successful fabrication of commodity 64 Mb DRAM chips and logic device and circuits on patterned SOI wafers is reported for the first time. The effect of SIMOX implantation and annealing on DRAMs in patterned SOI wafers is studied. Excellent yields and comparable performance of DRAM in bulk regions of the patterned SOI wafers are observed. The logic devices in the adjacent SOI area of the patterned wafer show the expected enhanced drive current. This approach enables SOI based embedded DRAM.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125632010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Breakdown measurements of ultra-thin SiO/sub 2/ at low voltage 超薄SiO/ sub2 /在低电压下击穿测量
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852783
J. Stathis, A. Vayshenker, P. Varekamp, E. Wu, C. Montrose, J. McKenna, D. DiMaria, L. Han, E. Cartier, R. Wachnik, B. Linder
{"title":"Breakdown measurements of ultra-thin SiO/sub 2/ at low voltage","authors":"J. Stathis, A. Vayshenker, P. Varekamp, E. Wu, C. Montrose, J. McKenna, D. DiMaria, L. Han, E. Cartier, R. Wachnik, B. Linder","doi":"10.1109/VLSIT.2000.852783","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852783","url":null,"abstract":"MOSFETs with oxide thickness from t/sub ox/=1.4 to 2.2nm have been stressed for times exceeding one year, at voltages in the range V/sub g/=1.9-4V. The data are compared with previous model calculations. The voltage acceleration of the charge-to-breakdown (Q/sub BD/) is explained in terms of a weak yet statistically significant voltage dependence of the critical defect density at breakdown (N/sup BD/), and a stronger than expected voltage dependence of the defect generation probability (P/sub g/) for the thinnest oxides studied.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129424802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Highly thermal-stable, plasma-polymerized BCB polymer film (k=2.6) for Cu dual-damascene interconnects 高度热稳定的等离子体聚合BCB聚合物薄膜(k=2.6)，用于铜双砷互连
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852752
J. Kawahara, K. Shiba, M. Tagami, M. Tada, S. Saito, T. Onodera, K. Kinoshita, M. Hiroi, A. Furuya, K. Kikuta, Y. Hayashi
{"title":"Highly thermal-stable, plasma-polymerized BCB polymer film (k=2.6) for Cu dual-damascene interconnects","authors":"J. Kawahara, K. Shiba, M. Tagami, M. Tada, S. Saito, T. Onodera, K. Kinoshita, M. Hiroi, A. Furuya, K. Kikuta, Y. Hayashi","doi":"10.1109/VLSIT.2000.852752","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852752","url":null,"abstract":"Highly thermal-stable, plasma-polymerized divinyl siloxane bis-benzocyclobutene (p-BCB)-polymer film is developed for Cu dual-damascene interconnects. The thermal stability of p-BCB is improved over 400/spl deg/C by higher deposition temperature, having high resistance to Cu diffusion at 400/spl deg/C-annealing. Lowering the RF plasma-power and the deposition pressure, the p-BCB film has smaller dielectric constant than the conventional spin-coating BCB (k=2.7). The p-BCB (k=2.6)/Cu interconnects reveal 46% delay reduction of CMOS ring oscillator to the conventional SiO/sub 2//Al ones. The p-BCB is proved as a strong candidate for Cu/low-k interconnects.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"45 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126410668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low temperature (<500/spl deg/C) SrTiO/sub 3/ capacitor process technology for embedded DRAM 嵌入式DRAM低温(<500/spl℃)SrTiO/sub - 3/电容器工艺技术
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852787
J. Nakahira, M. Kiyotoshi, S. Yamazaki, M. Nakabayashi, S. Niwa, K. Tsunoda, J. Lin, A. Shimada, M. Izuha, T. Aoyama, H. Tomita, K. Eguchi, K. Hieda
{"title":"Low temperature (<500/spl deg/C) SrTiO/sub 3/ capacitor process technology for embedded DRAM","authors":"J. Nakahira, M. Kiyotoshi, S. Yamazaki, M. Nakabayashi, S. Niwa, K. Tsunoda, J. Lin, A. Shimada, M. Izuha, T. Aoyama, H. Tomita, K. Eguchi, K. Hieda","doi":"10.1109/VLSIT.2000.852787","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852787","url":null,"abstract":"We have developed low temperature SrTiO/sub 3/ (ST) capacitor process for embedded DRAM. ST film deposited at 475/spl deg/C was crystallized without additional annealing. 0.53nm SiO/sub 2/ equivalent thickness (teq) ST capacitor with Ru electrodes was obtained. The leakage current of the concave structure capacitor was less than 1fA/cell at /spl plusmn/0.8V for 256K 3-dimensional (3D) capacitors fabricated by the low temperature ST process. ST capacitor process can satisfy demands on lower processing temperature and scalability to very thin dielectric layer with low leakage current.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127235966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliable and enhanced performances of sub-0.1 /spl mu/m pMOSFETs doped by low biased plasma doping 低偏置等离子体掺杂可提高0.1 /spl μ m以下pmosfet的性能
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852789
D. Lenoble, F. Arnaud, A. Grouillet, R. Liebert, S. Walther, S. Felch, Z. Fangi, M. Haond
{"title":"Reliable and enhanced performances of sub-0.1 /spl mu/m pMOSFETs doped by low biased plasma doping","authors":"D. Lenoble, F. Arnaud, A. Grouillet, R. Liebert, S. Walther, S. Felch, Z. Fangi, M. Haond","doi":"10.1109/VLSIT.2000.852789","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852789","url":null,"abstract":"For the first time, we include low biased plasma doping (LB PLAD) technique for extensions doping within an industrial 0.13 /spl mu/m CMOS process. By comparing to the Ultra-Low Energy Ion Implantation (B/sup +/ and BF/sub 2//sup +/) technique (ULE I/I), plasma doped devices exhibits improved Short Channel Effect (SCE) and subthreshold performances mostly attributed to the good junction characteristics (tradeoff junction depth (X/sub j/)/sheet resistance (R/sub s/)).","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123428140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) 用于千兆级片上系统(GSoC)全球互连的集成架构
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852822
P. Zarkesh-Ha, J. Meindl
{"title":"An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)","authors":"P. Zarkesh-Ha, J. Meindl","doi":"10.1109/VLSIT.2000.852822","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852822","url":null,"abstract":"An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) is presented using the models for global signal, clock, and power supply wiring networks. Based on the models for wiring resource demand, noise limit, and bandwidth requirement, an interconnect design plane is proposed. The new design plane demonstrates the limits imposed on global on-chip interconnect physical dimensions for future technology generations.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115017771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology] 基于传导带和价带电子和空穴隧道的栅极和衬底电流建模[CMOS技术]
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852824
Wen-Chin Lee, C. Hu
{"title":"Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology]","authors":"Wen-Chin Lee, C. Hu","doi":"10.1109/VLSIT.2000.852824","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852824","url":null,"abstract":"A model is proposed to quantify the tunneling currents through ultra-thin gate oxides. With a proper set of effective mass and barrier height, this new model can accurately predict the gate and substrate currents and all the subcomponents in dual-gate CMOS devices. This model can also be employed to extract T/sub ox/ for thin oxide from I-V data with 0.1/spl Aring/ sensitivity, where C-V extraction can be difficult or impossible.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123088936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 97
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