0.25 /spl mu/m使用模式化SOI合并批量DRAM和SOI逻辑

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852772

R. Hannon, S. Iyer, D. Sadana, J. Rice, H. Ho, B. Khan, S. Iyer

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引用次数: 3

摘要

首次报道了在SOI晶圆上成功制造商用64mb DRAM芯片和逻辑器件及电路。研究了SIMOX注入和退火对SOI图像化晶圆中dram性能的影响。在图像化SOI晶圆的大块区域中观察到优异的产量和相当的DRAM性能。在图像化晶片的相邻SOI区域的逻辑器件显示预期的增强驱动电流。这种方法使基于SOI的嵌入式DRAM成为可能。

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0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI

The successful fabrication of commodity 64 Mb DRAM chips and logic device and circuits on patterned SOI wafers is reported for the first time. The effect of SIMOX implantation and annealing on DRAMs in patterned SOI wafers is studied. Excellent yields and comparable performance of DRAM in bulk regions of the patterned SOI wafers are observed. The logic devices in the adjacent SOI area of the patterned wafer show the expected enhanced drive current. This approach enables SOI based embedded DRAM.

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来源期刊

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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