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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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Twin MONOS cell with dual control gates 双MONOS细胞与双控制门
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852794
Y. Hayashi, S. Ogura, T. Saito, T. Ogura
{"title":"Twin MONOS cell with dual control gates","authors":"Y. Hayashi, S. Ogura, T. Saito, T. Ogura","doi":"10.1109/VLSIT.2000.852794","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852794","url":null,"abstract":"A new twin MONOS cell for high density, high speed and low power program is presented having a proposed hard bit density of 3F/sup 2/ and soft-bit density of 1.5 F/sup 2/ with 2-bit multilevel storage, program speed of <1 usec and program current of /spl sim/10 uA/cell.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125326517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
SiGe heterojunctions in epitaxial vertical surrounding-gate MOSFETs 外延垂直围栅mosfet中的SiGe异质结
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852759
C. Date, J. Plummer
{"title":"SiGe heterojunctions in epitaxial vertical surrounding-gate MOSFETs","authors":"C. Date, J. Plummer","doi":"10.1109/VLSIT.2000.852759","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852759","url":null,"abstract":"Vertical MOSFETs are possible future architectures for memory cells as well as alternatives for conventional CMOS devices. The vertical channel allows growth of epitaxial structures, such as heterostructures, before the pillars are etched. We show how incorporation of SiGe heterostructures in vertical MOSFET devices can be used to delay the floating body effect or to modify hot carrier characteristics.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129142295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A highly versatile 0.18 /spl mu/m CMOS technology with dense embedded SRAM 一种高度通用的0.18 /spl μ m CMOS技术，具有密集的嵌入式SRAM
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852811
M. Bhat, S. Shi, P. Grudowski, C. Feng, B. Lee, R. Nagabushnam, J. Moench, C. Gunderson, P. Schani, L. Day, S. Bishop, H. Tian, J. Chung, C. Lage, J. Ellis, N. Herr, P. Gilbert, A. Das, F. Nkansah, M. Woo, M. Wilson, D. Derr, L. Terpolilli, K. Weidemann, R. Stout, A. Hamilton, T. Lii, F. Huang, K. Cox, J. Scott
{"title":"A highly versatile 0.18 /spl mu/m CMOS technology with dense embedded SRAM","authors":"M. Bhat, S. Shi, P. Grudowski, C. Feng, B. Lee, R. Nagabushnam, J. Moench, C. Gunderson, P. Schani, L. Day, S. Bishop, H. Tian, J. Chung, C. Lage, J. Ellis, N. Herr, P. Gilbert, A. Das, F. Nkansah, M. Woo, M. Wilson, D. Derr, L. Terpolilli, K. Weidemann, R. Stout, A. Hamilton, T. Lii, F. Huang, K. Cox, J. Scott","doi":"10.1109/VLSIT.2000.852811","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852811","url":null,"abstract":"Summary form only given. We report on a 3.3 V/2.5 V compatible, 1.5 V high performance dense CMOS SRAM technology utilizing a 2.74 um/sup 2/ 6-T bitcell. This 0.18 /spl mu/m CMOS process with a nominal 0.13 /spl mu/m gate poly and a 30 /spl Aring/ gate oxide utilizes aggressive interwell isolation, enhanced self-aligned local interconnect, low-K interlevel dielectric, and scaled copper metallization. In addition, the technology allows for low leakage, high density and SER resistant embedded SRAM applications by allowing integration of low leakage array transistors, buried channel pMOS loads, self-aligned contacts and triple well in the memory array. Finally, this integration includes a 70 /spl Aring//30 /spl Aring/ DGO technology for 3.3 V interfaces. High performance 6-T bitcell operation, 8 Mb stand-alone SRAM yield and high performance DSP circuit with 4 Mb embedded memory with this aggressively scaled bitcell has been successfully demonstrated. Cell currents of 85 /spl mu/A has been achieved for a supply voltage of 1.5 V while maintaining static noise margin in excess of 220 mV.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129187948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A compact FD-SOI MOSFETs fabrication process featuring Si/sub x/Ge/sub 1-x/ gate and damascene-dummy SAC 一种具有Si/sub -x/ Ge/sub -x/栅极和damascena dummy SAC的紧凑FD-SOI mosfet制造工艺
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852828
D. Hisamoto, T. Kachi, S. Tsujikawa, A. Miyauchi, K. Kusukawa, N. Sakuma, Y. Homma, N. Yokoyama, F. Ootsuka, T. Onai
{"title":"A compact FD-SOI MOSFETs fabrication process featuring Si/sub x/Ge/sub 1-x/ gate and damascene-dummy SAC","authors":"D. Hisamoto, T. Kachi, S. Tsujikawa, A. Miyauchi, K. Kusukawa, N. Sakuma, Y. Homma, N. Yokoyama, F. Ootsuka, T. Onai","doi":"10.1109/VLSIT.2000.852828","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852828","url":null,"abstract":"A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped Si/sub x/Ge/sub 1-x/ as a gate material, the adequate threshold voltage of FD-SOI was realized.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124514110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Direct measurement of V/sub th/ fluctuation caused by impurity positioning 直接测量杂质定位引起的V/sub /波动
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852800
Tetsu Tanaka, Tatsuya Usuki, Y. Momiyama, Toshihiro Sugii
{"title":"Direct measurement of V/sub th/ fluctuation caused by impurity positioning","authors":"Tetsu Tanaka, Tatsuya Usuki, Y. Momiyama, Toshihiro Sugii","doi":"10.1109/VLSIT.2000.852800","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852800","url":null,"abstract":"This paper studies a local fluctuation of channel impurity on the source edge. Our direct measurement successfully separates the local (intra-FET) and global (inter-FET) factors. The quite local region (/spl Lt/L/sub eff//spl times/W/sub eff/) significantly affects V/sub th/ distribution in a high V/sub d/, which exceeds the global factor in the smallest MOSFETs. The local fluctuation inevitably affects MOSFETs in SRAM cells even though global fluctuation is reduced by process optimization.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124638413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects 高性能80纳米门长SOI-CMOS技术，采用铜和极低k互连
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852819
K. Sukegawa, M. Yamaji, K. Yoshie, K. Furumochi, T. Maruyama, H. Morioka, N. Naori, T. Kubo, H. Kanata, M. Kai, S. Satoh, T. Izawa, K. Kubota
{"title":"High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects","authors":"K. Sukegawa, M. Yamaji, K. Yoshie, K. Furumochi, T. Maruyama, H. Morioka, N. Naori, T. Kubo, H. Kanata, M. Kai, S. Satoh, T. Izawa, K. Kubota","doi":"10.1109/VLSIT.2000.852819","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852819","url":null,"abstract":"High-performance 0.13-/spl mu/m CMOS logic technology has been developed using partially-depleted SOI transistors, EB lithography, and seven-layer copper dual-damascene interconnects with an organic very-low-k dielectric. The technology achieves 9-psec inverter delay at 1.3 V, a 60-m/spl Omega///spl square/ sheet resistance of interconnects, and a 30% smaller intra-layer capacitance than USG. This technology is applied to 1.5-GHz MPU chips.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116283782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Split gate cell with phonon assisted ballistic CHE injection 声子辅助弹道CHE注射的分栅细胞
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852796
T. Saito, S. Ogura, T. Ogura, T. Yuda, Y. Kawazu, M. Ikegami, A. Uchiyama, T. Ono
{"title":"Split gate cell with phonon assisted ballistic CHE injection","authors":"T. Saito, S. Ogura, T. Ogura, T. Yuda, Y. Kawazu, M. Ikegami, A. Uchiyama, T. Ono","doi":"10.1109/VLSIT.2000.852796","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852796","url":null,"abstract":"A planar channel split floating gate memory cell with an ultra short channel of <40 nm (within 3-4/spl times/ of the electron mean free path) is presented, in which high energy channel hot electrons generated by ballistic channel transport can be injected by phonon scattering with slight energy loss. This planar channel device can match the <1 /spl mu/s program speed of the previously reported step channel ballistic device at the same low voltages of Vd=5 V, Vcg=5 V. The structural differences between a planar and step channel are evaluated.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Practical benefits of the electromigration short-length effect, including a new design rule methodology and an electromigration resistant power grid with enhanced wireability 电迁移短长度效应的实际好处，包括一种新的设计规则方法和一个抗电迁移的电网，增强了可移植性
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852833
R. Wachnik, R. Filippi, T. Shaw, P. Lin
{"title":"Practical benefits of the electromigration short-length effect, including a new design rule methodology and an electromigration resistant power grid with enhanced wireability","authors":"R. Wachnik, R. Filippi, T. Shaw, P. Lin","doi":"10.1109/VLSIT.2000.852833","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852833","url":null,"abstract":"A simple first principles model is shown to accurately relate resistance saturation during electromigration to the current density and stripe length. Resistance saturation is found to be independent of temperature in the range 170-250/spl deg/C. The above observations allow for the development of a new design rule methodology. An electromigration resistant power grid may be designed which takes advantage of the short-length effect.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125598983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation 在0.10-/spl mu/m栅极CMOS制备中，超薄栅极氧化物掺入氮气增强NBTI
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852782
N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. Liu, R. Keller, T. Horiuchi
{"title":"NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation","authors":"N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. Liu, R. Keller, T. Horiuchi","doi":"10.1109/VLSIT.2000.852782","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852782","url":null,"abstract":"We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET with ultrathin gate oxide. It was experimentally demonstrated that the chemical reactions at the gate oxide/substrate interface and/or diffusion of hydrogen related species are the major cause of the NBTI. We also found that nitridation of gate oxide enhances NBTI. In order to suppress the NBTI, the density of hydrogen terminated silicon bond at the interface needs to be minimized. Thus, the concentration of nitrogen in thin gate oxide has to be optimized in terms of the reliability reduction due to NBTI.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125685450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 153
VLSI Symposium and silicon technology: a twenty year perspective 超大规模集成电路研讨会与硅技术:二十年展望
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852745
Y. El-Mansy
{"title":"VLSI Symposium and silicon technology: a twenty year perspective","authors":"Y. El-Mansy","doi":"10.1109/VLSIT.2000.852745","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852745","url":null,"abstract":"The VLSI Symposium was conceived in 1980 by a number of leading technologists from the U.S. and Japan. It was intended to be a forum for senior technology managers and experts to discuss the state of the then emerging VLSI technology and chart future roadmaps. This paper illustrates the technology advance during the life of the VLSI Symposium by contrasting state of the art technologies of the years 1981 and 2000.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115376818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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