A compact FD-SOI MOSFETs fabrication process featuring Si/sub x/Ge/sub 1-x/ gate and damascene-dummy SAC

Abstract

A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped Si/sub x/Ge/sub 1-x/ as a gate material, the adequate threshold voltage of FD-SOI was realized.