High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects

Abstract

High-performance 0.13-/spl mu/m CMOS logic technology has been developed using partially-depleted SOI transistors, EB lithography, and seven-layer copper dual-damascene interconnects with an organic very-low-k dielectric. The technology achieves 9-psec inverter delay at 1.3 V, a 60-m/spl Omega///spl square/ sheet resistance of interconnects, and a 30% smaller intra-layer capacitance than USG. This technology is applied to 1.5-GHz MPU chips.