高性能80纳米门长SOI-CMOS技术，采用铜和极低k互连

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852819

K. Sukegawa, M. Yamaji, K. Yoshie, K. Furumochi, T. Maruyama, H. Morioka, N. Naori, T. Kubo, H. Kanata, M. Kai, S. Satoh, T. Izawa, K. Kubota

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引用次数: 10

摘要

高性能的0.13-/spl mu/m CMOS逻辑技术采用部分耗尽的SOI晶体管，EB光刻和七层铜双damascene互连与有机极低k介电介质。该技术在1.3 V下实现了9 psec的逆变器延迟，互连电阻为60 m/spl ω ///spl平方/片，层内电容比USG小30%。该技术应用于1.5 ghz的微处理器芯片。

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High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects

High-performance 0.13-/spl mu/m CMOS logic technology has been developed using partially-depleted SOI transistors, EB lithography, and seven-layer copper dual-damascene interconnects with an organic very-low-k dielectric. The technology achieves 9-psec inverter delay at 1.3 V, a 60-m/spl Omega///spl square/ sheet resistance of interconnects, and a 30% smaller intra-layer capacitance than USG. This technology is applied to 1.5-GHz MPU chips.

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来源期刊

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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