一种具有Si/sub -x/ Ge/sub -x/栅极和damascena dummy SAC的紧凑FD-SOI mosfet制造工艺

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852828

D. Hisamoto, T. Kachi, S. Tsujikawa, A. Miyauchi, K. Kusukawa, N. Sakuma, Y. Homma, N. Yokoyama, F. Ootsuka, T. Onai

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引用次数: 1

摘要

介绍了一种紧凑的FD-SOI CMOS制作工艺和器件结构。一种新的大马士革假SAC工艺能够与超薄SOI层制造可靠的接触。结果表明，采用原位掺硼Si/sub -x/ Ge/sub - 1-x/作为栅极材料，可以实现FD-SOI的适当阈值电压。

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A compact FD-SOI MOSFETs fabrication process featuring Si/sub x/Ge/sub 1-x/ gate and damascene-dummy SAC

A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped Si/sub x/Ge/sub 1-x/ as a gate material, the adequate threshold voltage of FD-SOI was realized.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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