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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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A new cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating 一种可扩展BST电容器的新电池技术，使用大马士革形成的基座电极和[Pt-Ir]合金涂层
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852788
H. Itoh, Y. Tsunemine, A. Yutani, T. Okudaira, K. Kashihara, M. Inuishi, M. Yamamuka, T. Kawahara, T. Horikawa, T. Ohmori, S. Satoh
{"title":"A new cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating","authors":"H. Itoh, Y. Tsunemine, A. Yutani, T. Okudaira, K. Kashihara, M. Inuishi, M. Yamamuka, T. Kawahara, T. Horikawa, T. Ohmori, S. Satoh","doi":"10.1109/VLSIT.2000.852788","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852788","url":null,"abstract":"A scalable pedestal cell technology has been successfully developed for the BST capacitor by introducing the damascene scheme into the pedestal electrode formation and by employing [Pt-Ir] alloy for coating the pedestal electrode. With a PVD-BST liner as the blanket nucleating layer and as the barrier layer against the destructive oxidant, the MOCVD-BST functions in prime condition on the storage node developed.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116035109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.15 /spl mu/m CMOS foundry technology with 0.1 /spl mu/m devices for high performance applications 一种0.15 /spl μ m CMOS代工技术，具有0.1 /spl μ m器件，适用于高性能应用
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852803
C. H. Diaz, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, C. Hu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, C. Wang, C.C. Wang, J. Shih, H. Hsieh, H. Tao, S. Jang, M. Yu, S. Shue, B. Chen, T. Chang, C. Hou, B. Liew, K.H. Lee, Y.C. Sun
{"title":"A 0.15 /spl mu/m CMOS foundry technology with 0.1 /spl mu/m devices for high performance applications","authors":"C. H. Diaz, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, C. Hu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, C. Wang, C.C. Wang, J. Shih, H. Hsieh, H. Tao, S. Jang, M. Yu, S. Shue, B. Chen, T. Chang, C. Hou, B. Liew, K.H. Lee, Y.C. Sun","doi":"10.1109/VLSIT.2000.852803","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852803","url":null,"abstract":"This paper describes a leading-edge 0.15 /spl mu/m CMOS logic foundry technology family. Advanced core devices using 20 /spl Aring/ oxides for 1.2-1.5 V operation (L/sub G min/=0.1 /spl mu/m) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 /spl Aring/ oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 /spl Aring/ gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 /spl mu/m for M1 and 0.48 /spl mu/m for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 /spl mu/m/sup 2/ demonstrated in a 2Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127309037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric 采用铜互连和低k BEOL介电介质的高性能0.13 /spl mu/m SOI CMOS技术
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852818
Peter Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, Michael J. Hargrove, J. Herman, L. Lin, Randy W. Mann, Edward P. Maciejewski, Shreesh Narasimha, P. O'Neil, Stewart E. Rauch, D. Ryan, J. Toomey, Len Y. Tsou, P. Varekamp, R. Wachnik, T. Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, S. Crowder, C. Davis, R. Ferguson, Akihisa Sekiguchi, L. Su, R. Goldblatt, T. C. Chen
{"title":"A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric","authors":"Peter Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, Michael J. Hargrove, J. Herman, L. Lin, Randy W. Mann, Edward P. Maciejewski, Shreesh Narasimha, P. O'Neil, Stewart E. Rauch, D. Ryan, J. Toomey, Len Y. Tsou, P. Varekamp, R. Wachnik, T. Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, S. Crowder, C. Davis, R. Ferguson, Akihisa Sekiguchi, L. Su, R. Goldblatt, T. C. Chen","doi":"10.1109/VLSIT.2000.852818","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852818","url":null,"abstract":"This paper describes a 1.2V high performance 0.13 /spl mu/m generation SOI technology. Aggressive ground-rules and a tungsten damascene local interconnect render the densest 6T SRAM reported to date with a cell area of 2.16 /spl mu/m/sup 2/. This is accomplished with 248nm lithography, using optical proximity correction and resolution enhancement techniques on all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced low-k interlevel dielectric.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114556299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Copper distribution behavior near a SiO/sub 2//Si interface by low-temperature (<400/spl deg/C) annealing and its influence on electrical characteristics of MOS-capacitors 低温(<400/spl℃)退火处理下SiO/sub /Si界面附近铜的分布行为及其对mos电容器电特性的影响
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852754
K. Hozawa, T. Itoga, S. Isomae, J. Yugami, M. Ohkura
{"title":"Copper distribution behavior near a SiO/sub 2//Si interface by low-temperature (<400/spl deg/C) annealing and its influence on electrical characteristics of MOS-capacitors","authors":"K. Hozawa, T. Itoga, S. Isomae, J. Yugami, M. Ohkura","doi":"10.1109/VLSIT.2000.852754","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852754","url":null,"abstract":"The Cu redistribution behavior near a SiO/sub 2//Si interface after low temperature annealing is examined by using total reflection of X-ray fluorescence (TXRF) to simulate the effect of thermal budget in multi-level wiring processes. Cu atoms intentionally adsorbed on backside of the wafers were diffused and were once gettered at the gettering sites during high-temperature drive-in diffusion. However, after low-temperature annealing following the drive-in diffusion, Cu concentration of the Si surface was found to increase even in CZ wafers with intrinsic gettering process (IG). Cu atoms gettered in the vicinity of the SiO/sub 2//Si interface after drive-in diffusion are found to readily transport through the SiO/sub 2/ film and reach the SiO/sub 2/ surface during 400/spl deg/C annealing. This transport of Cu is found to cause degradation of thin SiO/sub 2/ film. The redistribution phenomenon during low-temperature annealing should be carefully controlled in order to realize highly reliable CMOS devices.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121122643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Ultra low energy arsenic implant limits on sheet resistance and junction depth 超低能砷植入对薄片电阻和结深的限制
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852790
R. Kasnavi, P. Griffin, J. Plummer
{"title":"Ultra low energy arsenic implant limits on sheet resistance and junction depth","authors":"R. Kasnavi, P. Griffin, J. Plummer","doi":"10.1109/VLSIT.2000.852790","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852790","url":null,"abstract":"We have investigated the limits on sheet resistance, junction depth and abruptness using ultra low energy As implants and RTA annealing. We report on anomalous diffusion of 1 keV arsenic implants where the same RTA anneal can result in a deeper junction compared to a 5 keV implant of similar dose. A range of anneal times and temperatures in an RTA from 1020C to 1175C, including spike anneals, have been studied. The effect of junction abruptness in reducing the external resistance of the S/D extension for these 5 and 1 keV As implants has been investigated. We show that because of a trade off between junction depth and sheet resistance limits, 1 keV As implants and RTA anneals cannot meet the technology roadmap requirements beyond 2005, though the junction abruptness will meet the requirements till 2011.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115844546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip 采用氟植入的三栅氧化物CMOS技术用于片上系统
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852804
Y. Goto, K. Imai, E. Hasegawa, T. Ohashi, N. Kimizuka, T. Toda, N. Hamanaka, T. Horiuchi
{"title":"A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip","authors":"Y. Goto, K. Imai, E. Hasegawa, T. Ohashi, N. Kimizuka, T. Toda, N. Hamanaka, T. Horiuchi","doi":"10.1109/VLSIT.2000.852804","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852804","url":null,"abstract":"We have developed a triple gate oxide CMOS technology that integrates 0.10-/spl mu/m gate length 1.2-V high-speed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and successfully reduced the gate leakage current by 1.5 orders of magnitude.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"348 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122169862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A novel 1T1C capacitor structure for high density FRAM 用于高密度FRAM的新型1T1C电容器结构
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852758
N. Jang, Y.J. Song, H.H. Kim, D. Jung, B. Koo, S.Y. Lee, S. Joo, K.M. Lee, K. Kim
{"title":"A novel 1T1C capacitor structure for high density FRAM","authors":"N. Jang, Y.J. Song, H.H. Kim, D. Jung, B. Koo, S.Y. Lee, S. Joo, K.M. Lee, K. Kim","doi":"10.1109/VLSIT.2000.852758","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852758","url":null,"abstract":"In this paper, an etching damage-free 4 Mb ferroelectric random access memory (FRAM) integration technology was for the first time developed using ferroelectric (FE) hole capacitor structure. Since the PZT capacitors are not etched, no etching damage was generated in the novel capacitor structure. The etching process issue, which is one of most critical obstacles for scaling down FRAM device, is completely resolved by using this novel FE hole structure. Therefore, the novel integration technology strongly promises to provide a reliable scaling down of FRAM device beyond 0.25 /spl mu/m technology generation.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129155319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Characteristics of Al/sub 2/O/sub 3/ gate dielectric prepared by atomic layer deposition for giga scale CMOS DRAM devices 千兆级CMOS DRAM器件用原子层沉积Al/sub 2/O/sub 3/栅极介质的特性
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852763
Dae-gyu Park, Heung-Jae Cho, C. Lim, I. Yeo, J. Roh, Chung-Tae Kim, J. Hwang
{"title":"Characteristics of Al/sub 2/O/sub 3/ gate dielectric prepared by atomic layer deposition for giga scale CMOS DRAM devices","authors":"Dae-gyu Park, Heung-Jae Cho, C. Lim, I. Yeo, J. Roh, Chung-Tae Kim, J. Hwang","doi":"10.1109/VLSIT.2000.852763","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852763","url":null,"abstract":"This paper demonstrates characteristics of Al/sub 2/O/sub 3/ gate dielectric prepared by atomic layer deposition (ALD) for giga scale CMOS DRAM devices. Interface state density /spl sim/7/spl times/10/sup 10/ eV/sup -1/ cm/sup -2/ near the midgap and excellent reliability with a low gate leakage current were attained from Al/sub 2/O/sub 3//Si MOS system. p/nMOSFETs characteristics in terms of current drivability, transconductance (Gm), and subthreshold swing are described.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"126 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134553997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 0.17 /spl mu/m embedded DRAM technology with 0.23 /spl mu/m/sup 2/ cell size and advanced CMOS logic 采用0.17 /spl mu/m的嵌入式DRAM技术，单元尺寸为0.23 /spl mu/m/sup 2/，采用先进的CMOS逻辑
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852771
H. Wurzer, I. Feldner, W. Graf, G. Curello, J. Faul, D. Weber, A. Kieslich
{"title":"A 0.17 /spl mu/m embedded DRAM technology with 0.23 /spl mu/m/sup 2/ cell size and advanced CMOS logic","authors":"H. Wurzer, I. Feldner, W. Graf, G. Curello, J. Faul, D. Weber, A. Kieslich","doi":"10.1109/VLSIT.2000.852771","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852771","url":null,"abstract":"A new 0.17 /spl mu/m embedded DRAM (eDRAM) technology is presented. Basing on a DRAM process with a cell size of 0.23 /spl mu/m/sup 2/ CMOS logic has been improved by introducing a new isolation concept called deep trench isolation and an aggressive device scaling. This is completed by a 6-level AlCu RIE metalization. This concept enables a system-on-a-chip (SOC) solution up to several hundred Mbits DRAM capacity on smallest chip size and highest yield perspectives.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127574294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advanced SOI-MOSFETs with strained-Si channel for high speed CMOS-electron/hole mobility enhancement 具有应变si通道的先进soi - mosfet用于高速cmos电子/空穴迁移率增强
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852829
T. Mizuno, N. Sugiyama, H. Satake, S. Takagi
{"title":"Advanced SOI-MOSFETs with strained-Si channel for high speed CMOS-electron/hole mobility enhancement","authors":"T. Mizuno, N. Sugiyama, H. Satake, S. Takagi","doi":"10.1109/VLSIT.2000.852829","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852829","url":null,"abstract":"In this work, we propose strained-Si MOSFETs on double-layer SiGe films with different Ge contents as high performance p-MOSFETs. Actually, we demonstrate high hole mobility enhancement (45% against that in control-SOI MOSFETs and 30% against the universal mobility) in strained-SOI p-MOSFETs including double-hetero structures (Si/sub 0.82/Ge/sub 0.18//Si/sub 0.9/Ge/sub 0.1/) for the first time. Moreover, it is also demonstrated that the electron mobility in n-channel strained-SOI MOSFETs is enhanced by about 60%, using single SiGe layer with the Ge content of as low as 10%.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116488635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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