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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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A 180 nm copper/low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications 采用双栅氧化物的180nm铜/低k CMOS技术，针对低功耗和低成本消费级无线应用进行了优化
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852805
G. Yeap, F. Nkansah, J. Chen, S. Jallepalli, D. Pham, T. Lii, A. Nangia, P. Le, D. Hall, D. Menke, J. Sun, A. Das, P. Gilbert, F. Huang, J. Sturtevant, K. Green, J. Lu, J. Benavidas, E. Banks, J. Chung, C. Lage
{"title":"A 180 nm copper/low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications","authors":"G. Yeap, F. Nkansah, J. Chen, S. Jallepalli, D. Pham, T. Lii, A. Nangia, P. Le, D. Hall, D. Menke, J. Sun, A. Das, P. Gilbert, F. Huang, J. Sturtevant, K. Green, J. Lu, J. Benavidas, E. Banks, J. Chung, C. Lage","doi":"10.1109/VLSIT.2000.852805","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852805","url":null,"abstract":"We report a 180 nm CMOS technology with dual gate oxide (DGO) optimized for low power and low cost consumer wireless products. To minimize cost and maximize manufacturability, super halo is used for the first time to integrate 70 /spl Aring/ 2.5-3.3 V I/O devices with either 130 nm/29 /spl Aring/ or 150 nm/35 /spl Aring/ low leakage (LL) p/spl Aring///spl mu/m devices, eliminating three normally-required masks. Core LL devices optimized for 1.5 V and 1.8 V are available to maximize circuit design compatibility and IP reuse. Both LL devices yield superior performance, and less I/sub on//I/sub off/ sensitivity vs. gate-length control for robust manufacturing as compared to recently reported LL devices. This technology also features an all-layer copper/low-k interlayer dielectric backend for speed improvement and dynamic power reduction.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121604000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias 在具有正衬底偏压的nmosfet中，俄歇复合增强了热载子降解
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852798
L. Chiang, C.W. Tsai, T. Wang, U.C. Liu, M. Wang, L. Hsia
{"title":"Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias","authors":"L. Chiang, C.W. Tsai, T. Wang, U.C. Liu, M. Wang, L. Hsia","doi":"10.1109/VLSIT.2000.852798","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852798","url":null,"abstract":"Enhanced hot carrier degradation is observed in DTMOS-like operation mode. This phenomenon is attributed to Auger recombination assisted hot electron process. Measured hot electron gate current and light emission spectrum in nMOSFETs provide evidence that the high-energy tail of channel electrons is increased by the application of a positive substrate bias. As opposed to conventional hot carrier degradation, the Auger enhanced degradation exhibits positive temperature dependence and is more significant at low drain bias.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124280360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dual-metal gate technology for deep-submicron CMOS transistors 深亚微米CMOS晶体管双金属栅极技术
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852774
Q. Lu, Y. Yeo, P. Ranade, H. Takeuchi, T. King, C. Hu, S.C. Song, H. Luan, D. Kwong
{"title":"Dual-metal gate technology for deep-submicron CMOS transistors","authors":"Q. Lu, Y. Yeo, P. Ranade, H. Takeuchi, T. King, C. Hu, S.C. Song, H. Luan, D. Kwong","doi":"10.1109/VLSIT.2000.852774","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852774","url":null,"abstract":"Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122661255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
0.18 um modular triple self-aligned embedded split-gate flash memory 0.18 um模块化三自对准嵌入式分栅闪存
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852793
R. Mih, J. Harrington, K. Houlihan, H. Lee, K. Chan, J. Johnson, Bomy Chen, Jiang Yan, A. Schmidt, C. Gruensfelder, Kisang Kim, D. Shum, C. Lo, D. Lee, A. Levi, C. Lam
{"title":"0.18 um modular triple self-aligned embedded split-gate flash memory","authors":"R. Mih, J. Harrington, K. Houlihan, H. Lee, K. Chan, J. Johnson, Bomy Chen, Jiang Yan, A. Schmidt, C. Gruensfelder, Kisang Kim, D. Shum, C. Lo, D. Lee, A. Levi, C. Lam","doi":"10.1109/VLSIT.2000.852793","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852793","url":null,"abstract":"A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122760708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
T/sub BD/ prediction from measurements at low field and room temperature using a new estimator 使用新的估计器从低场和室温测量中预测T/sub / BD/
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852832
A. Ghetti, J. Bude, G. Weber
{"title":"T/sub BD/ prediction from measurements at low field and room temperature using a new estimator","authors":"A. Ghetti, J. Bude, G. Weber","doi":"10.1109/VLSIT.2000.852832","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852832","url":null,"abstract":"We present a new method to predict oxide breakdown from measurements at low voltage and room temperature. The method is based on tunneling into interface states (TEDit). We show that TEDit correlates to breakdown. Then we exploit this correlation to predict oxide lifetime.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125449065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Development of CVD-Ru/Ta/sub 2/O/sub 5//CVD-TiN capacitor for multigigabit-scale DRAM generation 千兆级DRAM用CVD-Ru/Ta/sub 2/O/sub 5//CVD-TiN电容的研制
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852785
Wan-Don Kim, Jin Woon Kim, Seok-jun Won, S. Nam, B. Nam, C. Yoo, Y. Park, Sang In Lee, M. Lee
{"title":"Development of CVD-Ru/Ta/sub 2/O/sub 5//CVD-TiN capacitor for multigigabit-scale DRAM generation","authors":"Wan-Don Kim, Jin Woon Kim, Seok-jun Won, S. Nam, B. Nam, C. Yoo, Y. Park, Sang In Lee, M. Lee","doi":"10.1109/VLSIT.2000.852785","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852785","url":null,"abstract":"We have investigated the electrical properties of metal/Ta/sub 2/O/sub 5//metal (MIM-Ta/sub 2/O/sub 5/) capacitor for multigigabit-scale DRAMs. CVD-TiN film was used as a bottom electrode, whereas PVD-TiN, CVD-TiN and CVD-Ru metals were compared for a top electrode. Our results, including electrical properties and step coverage, showed that a CVD-Ru film is the most promising top electrode material. Based on this result, a CVD-Ru/Ta/sub 2/O/sub 5//CVD-TiN capacitor with cylinder-type storage node was developed, and the cell capacitance of 40fF/cell with the leakage current of 0.1fA/cell at /spl plusmn/1 V applied voltage was accomplished.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Transistor on capacitor (TOC) cell with quarter pitch layout for 0.13 /spl mu/m DRAMs and beyond 晶体管电容(TOC)电池与四分之一间距布局0.13 /spl mu/m dram及更高
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852778
M. Sato, S. Ishibashi, T. Kajiyama, M. Sakuma, I. Mizushima, Y. Tsunashima, F. Shoji, H. Yano, A. Nitayama, T. Hamamoto
{"title":"Transistor on capacitor (TOC) cell with quarter pitch layout for 0.13 /spl mu/m DRAMs and beyond","authors":"M. Sato, S. Ishibashi, T. Kajiyama, M. Sakuma, I. Mizushima, Y. Tsunashima, F. Shoji, H. Yano, A. Nitayama, T. Hamamoto","doi":"10.1109/VLSIT.2000.852778","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852778","url":null,"abstract":"We present a new trench type cell, transistor on capacitor (TOC) cell with 1/4 pitch layout. Two kinds of new idea have been implemented. One is that the density of the trench capacitor is closest packed by introducing 1/4 pitch layout. The other is that the transfer transistor is fabricated over the trench capacitor by introducing the newly developed epitaxial growth and Chemical Mechanical Polish (CMP) technologies. As a result, trench opening can be enlarged without reducing the gate length of the transfer transistor.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115534308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 70 nm gate length CMOS technology with 1.0 V operation 一个70 nm栅长CMOS技术与1.0 V工作
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852750
A. Ono, K. Fukasaku, T. Matsuda, T. Fukai, N. Ikezawa, K. Imai, T. Horiuchi
{"title":"A 70 nm gate length CMOS technology with 1.0 V operation","authors":"A. Ono, K. Fukasaku, T. Matsuda, T. Fukai, N. Ikezawa, K. Imai, T. Horiuchi","doi":"10.1109/VLSIT.2000.852750","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852750","url":null,"abstract":"A 70-nm gate length CMOS technology for 1.0 V operation has been developed. This technology realizes high performance CMOS roadmap trend and utilizes sub-1 keV ion implantation for source/drain extension formations, quick-cooling RTA process, and ultra-thin gate dielectrics of 1.3 nm. The thickness of the gate dielectrics has been optimized in terms of both the I/sub ON/-I/sub OFF/, tradeoff and gate delay metrics. Obtained I/sub D//sup SAT/ for nMOS and pMOS are 723 /spl mu/A//spl mu/m (I/sub OFF/=16 nA//spl mu/m) and 290 /spl mu/A//spl mu/m (I/sub OFF/=20 nA//spl mu/m), respectively.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127002758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Copper contamination induced degradation of MOSFET characteristics and reliability 铜污染导致MOSFET特性和可靠性退化
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852755
M. Inohara, H. Sakurai, T. Yamaguchi, H. Tomita, T. Iijima, H. Oyamatsu, T. Nakayama, H. Yoshimura, Y. Toyoshima
{"title":"Copper contamination induced degradation of MOSFET characteristics and reliability","authors":"M. Inohara, H. Sakurai, T. Yamaguchi, H. Tomita, T. Iijima, H. Oyamatsu, T. Nakayama, H. Yoshimura, Y. Toyoshima","doi":"10.1109/VLSIT.2000.852755","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852755","url":null,"abstract":"MOSFET electrical characteristics and reliability impact with copper contamination is examined and some degradation modes are inspected. The mechanism of degradation is explained by increase of carrier trap sites in gate silicon oxide. The permissive contamination level of copper in device region is indicated by comparison between two different contamination level samples.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129803431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A conformal ruthenium electrode for MIM capacitors in Gbit DRAMs using the CVD technology based on oxygen-controlled surface reaction 基于氧控表面反应的CVD技术制备了用于gb dram中MIM电容器的共形钌电极
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852786
M. Hiratani, T. Nabatame, Y. Matsui, Y. Shimamoto, Y. Sasago, Y. Nakamura, Y. Ohji, I. Asano, S. Kimura
{"title":"A conformal ruthenium electrode for MIM capacitors in Gbit DRAMs using the CVD technology based on oxygen-controlled surface reaction","authors":"M. Hiratani, T. Nabatame, Y. Matsui, Y. Shimamoto, Y. Sasago, Y. Nakamura, Y. Ohji, I. Asano, S. Kimura","doi":"10.1109/VLSIT.2000.852786","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852786","url":null,"abstract":"We have developed a novel CVD-Ru technique, clarified the growth mechanism and fabricated BST capacitors. The growth mechanism is dominated by the surface reaction which is rate-determined by the oxygen supply. Well-tuned conditions enable fabrication of any type of storage node: a concave type with a uniform 20-nm film thickness and a pillar type from a buried film. The electrode/BST interface is degraded by the reduction-oxidation reaction during the Ru-CVD, but post-annealing restores the ideal I-V characteristics.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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