一个70 nm栅长CMOS技术与1.0 V工作

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852750

A. Ono, K. Fukasaku, T. Matsuda, T. Fukai, N. Ikezawa, K. Imai, T. Horiuchi

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引用次数: 14

摘要

开发了一种用于1.0 V工作的70 nm栅长CMOS技术。该技术实现了高性能CMOS的发展趋势，采用了sub-1 keV离子注入源/漏扩展层、快速冷却RTA工艺和1.3 nm的超薄栅极电介质。栅极电介质的厚度在I/sub ON/ I/sub OFF/、权衡和栅极延迟指标方面进行了优化。得到nMOS和pMOS的I/sub D//sup SAT/分别为723 /spl mu/A//spl mu/m (I/sub OFF/=16 nA//spl mu/m)和290 /spl mu/A//spl mu/m (I/sub OFF/=20 nA//spl mu/m)。

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A 70 nm gate length CMOS technology with 1.0 V operation

A 70-nm gate length CMOS technology for 1.0 V operation has been developed. This technology realizes high performance CMOS roadmap trend and utilizes sub-1 keV ion implantation for source/drain extension formations, quick-cooling RTA process, and ultra-thin gate dielectrics of 1.3 nm. The thickness of the gate dielectrics has been optimized in terms of both the I/sub ON/-I/sub OFF/, tradeoff and gate delay metrics. Obtained I/sub D//sup SAT/ for nMOS and pMOS are 723 /spl mu/A//spl mu/m (I/sub OFF/=16 nA//spl mu/m) and 290 /spl mu/A//spl mu/m (I/sub OFF/=20 nA//spl mu/m), respectively.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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