M. Inohara, H. Sakurai, T. Yamaguchi, H. Tomita, T. Iijima, H. Oyamatsu, T. Nakayama, H. Yoshimura, Y. Toyoshima
{"title":"铜污染导致MOSFET特性和可靠性退化","authors":"M. Inohara, H. Sakurai, T. Yamaguchi, H. Tomita, T. Iijima, H. Oyamatsu, T. Nakayama, H. Yoshimura, Y. Toyoshima","doi":"10.1109/VLSIT.2000.852755","DOIUrl":null,"url":null,"abstract":"MOSFET electrical characteristics and reliability impact with copper contamination is examined and some degradation modes are inspected. The mechanism of degradation is explained by increase of carrier trap sites in gate silicon oxide. The permissive contamination level of copper in device region is indicated by comparison between two different contamination level samples.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Copper contamination induced degradation of MOSFET characteristics and reliability\",\"authors\":\"M. Inohara, H. Sakurai, T. Yamaguchi, H. Tomita, T. Iijima, H. Oyamatsu, T. Nakayama, H. Yoshimura, Y. Toyoshima\",\"doi\":\"10.1109/VLSIT.2000.852755\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"MOSFET electrical characteristics and reliability impact with copper contamination is examined and some degradation modes are inspected. The mechanism of degradation is explained by increase of carrier trap sites in gate silicon oxide. The permissive contamination level of copper in device region is indicated by comparison between two different contamination level samples.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"129 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852755\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852755","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Copper contamination induced degradation of MOSFET characteristics and reliability
MOSFET electrical characteristics and reliability impact with copper contamination is examined and some degradation modes are inspected. The mechanism of degradation is explained by increase of carrier trap sites in gate silicon oxide. The permissive contamination level of copper in device region is indicated by comparison between two different contamination level samples.