R. Mih, J. Harrington, K. Houlihan, H. Lee, K. Chan, J. Johnson, Bomy Chen, Jiang Yan, A. Schmidt, C. Gruensfelder, Kisang Kim, D. Shum, C. Lo, D. Lee, A. Levi, C. Lam
{"title":"0.18 um模块化三自对准嵌入式分栅闪存","authors":"R. Mih, J. Harrington, K. Houlihan, H. Lee, K. Chan, J. Johnson, Bomy Chen, Jiang Yan, A. Schmidt, C. Gruensfelder, Kisang Kim, D. Shum, C. Lo, D. Lee, A. Levi, C. Lam","doi":"10.1109/VLSIT.2000.852793","DOIUrl":null,"url":null,"abstract":"A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"0.18 um modular triple self-aligned embedded split-gate flash memory\",\"authors\":\"R. Mih, J. Harrington, K. Houlihan, H. Lee, K. Chan, J. Johnson, Bomy Chen, Jiang Yan, A. Schmidt, C. Gruensfelder, Kisang Kim, D. Shum, C. Lo, D. Lee, A. Levi, C. Lam\",\"doi\":\"10.1109/VLSIT.2000.852793\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"201 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852793\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852793","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
0.18 um modular triple self-aligned embedded split-gate flash memory
A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.
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