采用双栅氧化物的180nm铜/低k CMOS技术,针对低功耗和低成本消费级无线应用进行了优化

G. Yeap, F. Nkansah, J. Chen, S. Jallepalli, D. Pham, T. Lii, A. Nangia, P. Le, D. Hall, D. Menke, J. Sun, A. Das, P. Gilbert, F. Huang, J. Sturtevant, K. Green, J. Lu, J. Benavidas, E. Banks, J. Chung, C. Lage
{"title":"采用双栅氧化物的180nm铜/低k CMOS技术,针对低功耗和低成本消费级无线应用进行了优化","authors":"G. Yeap, F. Nkansah, J. Chen, S. Jallepalli, D. Pham, T. Lii, A. Nangia, P. Le, D. Hall, D. Menke, J. Sun, A. Das, P. Gilbert, F. Huang, J. Sturtevant, K. Green, J. Lu, J. Benavidas, E. Banks, J. Chung, C. Lage","doi":"10.1109/VLSIT.2000.852805","DOIUrl":null,"url":null,"abstract":"We report a 180 nm CMOS technology with dual gate oxide (DGO) optimized for low power and low cost consumer wireless products. To minimize cost and maximize manufacturability, super halo is used for the first time to integrate 70 /spl Aring/ 2.5-3.3 V I/O devices with either 130 nm/29 /spl Aring/ or 150 nm/35 /spl Aring/ low leakage (LL) p/spl Aring///spl mu/m devices, eliminating three normally-required masks. Core LL devices optimized for 1.5 V and 1.8 V are available to maximize circuit design compatibility and IP reuse. Both LL devices yield superior performance, and less I/sub on//I/sub off/ sensitivity vs. gate-length control for robust manufacturing as compared to recently reported LL devices. This technology also features an all-layer copper/low-k interlayer dielectric backend for speed improvement and dynamic power reduction.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 180 nm copper/low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications\",\"authors\":\"G. Yeap, F. Nkansah, J. Chen, S. Jallepalli, D. Pham, T. Lii, A. Nangia, P. Le, D. Hall, D. Menke, J. Sun, A. Das, P. Gilbert, F. Huang, J. Sturtevant, K. Green, J. Lu, J. Benavidas, E. Banks, J. Chung, C. Lage\",\"doi\":\"10.1109/VLSIT.2000.852805\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report a 180 nm CMOS technology with dual gate oxide (DGO) optimized for low power and low cost consumer wireless products. To minimize cost and maximize manufacturability, super halo is used for the first time to integrate 70 /spl Aring/ 2.5-3.3 V I/O devices with either 130 nm/29 /spl Aring/ or 150 nm/35 /spl Aring/ low leakage (LL) p/spl Aring///spl mu/m devices, eliminating three normally-required masks. Core LL devices optimized for 1.5 V and 1.8 V are available to maximize circuit design compatibility and IP reuse. Both LL devices yield superior performance, and less I/sub on//I/sub off/ sensitivity vs. gate-length control for robust manufacturing as compared to recently reported LL devices. This technology also features an all-layer copper/low-k interlayer dielectric backend for speed improvement and dynamic power reduction.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852805\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852805","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

我们报告了一种针对低功耗和低成本消费无线产品优化的180nm双栅氧化物(DGO) CMOS技术。为了最大限度地降低成本和最大限度地提高可制造性,首次使用超级光晕将70 /spl Aring/ 2.5-3.3 V I/O器件与130 nm/29 /spl Aring/或150 nm/35 /spl Aring/低泄漏(LL) p/spl Aring///spl mu/m器件集成在一起,消除了三个通常需要的掩模。为1.5 V和1.8 V优化的Core LL器件可最大限度地提高电路设计兼容性和IP重用。与最近报道的LL器件相比,两种LL器件都具有卓越的性能,并且与栅极长度控制相比,具有更少的I/sub on//I/sub off/灵敏度,从而实现稳健的制造。该技术还具有全层铜/低k层间介电后端,用于提高速度和降低动态功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 180 nm copper/low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications
We report a 180 nm CMOS technology with dual gate oxide (DGO) optimized for low power and low cost consumer wireless products. To minimize cost and maximize manufacturability, super halo is used for the first time to integrate 70 /spl Aring/ 2.5-3.3 V I/O devices with either 130 nm/29 /spl Aring/ or 150 nm/35 /spl Aring/ low leakage (LL) p/spl Aring///spl mu/m devices, eliminating three normally-required masks. Core LL devices optimized for 1.5 V and 1.8 V are available to maximize circuit design compatibility and IP reuse. Both LL devices yield superior performance, and less I/sub on//I/sub off/ sensitivity vs. gate-length control for robust manufacturing as compared to recently reported LL devices. This technology also features an all-layer copper/low-k interlayer dielectric backend for speed improvement and dynamic power reduction.
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