Q. Lu, Y. Yeo, P. Ranade, H. Takeuchi, T. King, C. Hu, S.C. Song, H. Luan, D. Kwong
{"title":"深亚微米CMOS晶体管双金属栅极技术","authors":"Q. Lu, Y. Yeo, P. Ranade, H. Takeuchi, T. King, C. Hu, S.C. Song, H. Luan, D. Kwong","doi":"10.1109/VLSIT.2000.852774","DOIUrl":null,"url":null,"abstract":"Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"47","resultStr":"{\"title\":\"Dual-metal gate technology for deep-submicron CMOS transistors\",\"authors\":\"Q. Lu, Y. Yeo, P. Ranade, H. Takeuchi, T. King, C. Hu, S.C. Song, H. Luan, D. Kwong\",\"doi\":\"10.1109/VLSIT.2000.852774\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"47\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852774\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dual-metal gate technology for deep-submicron CMOS transistors
Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.