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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices 重新审视可扩展性:100纳米PD-SOI晶体管及其对50纳米器件的影响
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852826
K. Mistry, T. Ghani, Mark Armstrong, S. Tyagi, P. Packan, Scott E. Thompson, S. Yu, M. Bohr
{"title":"Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices","authors":"K. Mistry, T. Ghani, Mark Armstrong, S. Tyagi, P. Packan, Scott E. Thompson, S. Yu, M. Bohr","doi":"10.1109/VLSIT.2000.852826","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852826","url":null,"abstract":"We describe 100 nm gate length PD-SOI transistors with the best SOI I/sub on/-I/sub off/ characteristics reported for the 0.18 /spl mu/m technology generation. SOI inverter delay is 7.4 ps at Vdd=1.5 V and L/sub gate/=100 nm. Inverter delays show 16% (fanout=1) and 8% Vdd(V) (fanout=4) improvement over comparable bulk CMOS. Scaling analysis for PD-SOI shows a reduced role for junction capacitance and an increased history effect for scaled devices, so that SOI has significantly diminished performance gain relative to bulk CMOS for 50 nm devices (0.1 /spl mu/m generation).","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123134647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Limits of gate-oxide scaling in nano-transistors 纳米晶体管栅氧化结垢的限制
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852781
B. Yu, H. Wang, C. Riccobene, Q. Xiang, M. Lin
{"title":"Limits of gate-oxide scaling in nano-transistors","authors":"B. Yu, H. Wang, C. Riccobene, Q. Xiang, M. Lin","doi":"10.1109/VLSIT.2000.852781","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852781","url":null,"abstract":"This paper explores the ultimate scaling limit of gate oxide due to MOSFET gate leakage and device performance. The limit on Tox reduction with respect to gate leakage tolerance is considered by the concept of \"dynamic\" gate leakage in nano-scale MOSFET's. Tox scaling is also limited by transistor performance degradation due to the loss of inversion layer charge through gate leakage and the degradation of carrier mobility in the channel from increased scattering. All the three effects are investigated experimentally on CMOS devices with gate length down to 50 nm and gate Tox down to 12 A. The minimum Tox is proposed and the implications on voltage scaling, high-k gate dielectrics and low-temperature CMOS are discussed.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130655596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
MISS tunnel diode: a capacitorless 4F/sup 2/ memory cell for sub-0.1 /spl mu/m era MISS隧道二极管:无电容4F/sup /存储单元，功率低于0.1 /spl mu/m
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852756
H. Matsuoka, T. Sakata, S. Kimura
{"title":"MISS tunnel diode: a capacitorless 4F/sup 2/ memory cell for sub-0.1 /spl mu/m era","authors":"H. Matsuoka, T. Sakata, S. Kimura","doi":"10.1109/VLSIT.2000.852756","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852756","url":null,"abstract":"To develop a capacitorless 4F/sup 2/ memory cell (F: DRAM half pitch) for the sub-0.1 /spl mu/m era, we propose using the MISS tunnel diode, having a simple structure consisting of metal/insulator/p-type Si/n-type Si. We have demonstrated its feasibility for the first time by extensively studying its transport properties.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132540756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances 多SiGe井:一种改善NMOS和PMOS性能的新通道架构
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852797
J. Alieu, T. Skotnicki, E. Josse, J. Regolini, G. Brémond
{"title":"Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances","authors":"J. Alieu, T. Skotnicki, E. Josse, J. Regolini, G. Brémond","doi":"10.1109/VLSIT.2000.852797","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852797","url":null,"abstract":"We present, for the first time, multiple SiGe quantum wells as a new channel architecture allowing increased performances for both NMOS and PMOS short channel transistors. We show that interleaved Si layers are strained as well as SiGe layers which strongly increases both electron and hole mobilities. Comparing multiple well and pure Si epitaxial channel devices, we demonstrate the ability of our structure to better control SCE for both NMOS and PMOS.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116669200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Gate oxide breakdown under Current Limited Constant Voltage Stress 栅极氧化物在电流限制恒压应力下击穿
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852830
B. Linder, J. Stathis, R. Wachnik, E. Wu, S. Cohen, A. Ray, A. Vayshenker
{"title":"Gate oxide breakdown under Current Limited Constant Voltage Stress","authors":"B. Linder, J. Stathis, R. Wachnik, E. Wu, S. Cohen, A. Ray, A. Vayshenker","doi":"10.1109/VLSIT.2000.852830","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852830","url":null,"abstract":"Ultra-thin oxide reliability has become an important issue in integrated circuit scaling. Present reliability methodology stresses oxides with a low impedance voltage source. This, though, does not represent the stress under circuit configurations, in which transistors are driven by other transistors. A Current Limited Constant Voltage Stress simulates circuit stress well. Limiting the current during the breakdown event reduces the post-breakdown conduction. Limiting the current to a sufficiently low value may prevent device failure, altogether.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126869195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics 具有Co硅化源极/漏极和高k栅极电介质的大马士革金属栅极mosfet
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852773
K. Matsuo, T. Saito, A. Yagishita, T. Iinuma, A. Murakoshi, K. Nakajima, S. Omoto, K. Suguro
{"title":"Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics","authors":"K. Matsuo, T. Saito, A. Yagishita, T. Iinuma, A. Murakoshi, K. Nakajima, S. Omoto, K. Suguro","doi":"10.1109/VLSIT.2000.852773","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852773","url":null,"abstract":"Damascene metal gate MOSFETs with Co silicided source/drain and high-k dielectrics were successfully formed without agglomeration of CoSi/sub 2/ films. Good transistor characteristics were reproducibly obtained and shorter inverter delay was confirmed by 151 stage CMOS ring oscillators.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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