Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices

Abstract

We describe 100 nm gate length PD-SOI transistors with the best SOI I/sub on/-I/sub off/ characteristics reported for the 0.18 /spl mu/m technology generation. SOI inverter delay is 7.4 ps at Vdd=1.5 V and L/sub gate/=100 nm. Inverter delays show 16% (fanout=1) and 8% Vdd(V) (fanout=4) improvement over comparable bulk CMOS. Scaling analysis for PD-SOI shows a reduced role for junction capacitance and an increased history effect for scaled devices, so that SOI has significantly diminished performance gain relative to bulk CMOS for 50 nm devices (0.1 /spl mu/m generation).