MISS tunnel diode: a capacitorless 4F/sup 2/ memory cell for sub-0.1 /spl mu/m era

Abstract

To develop a capacitorless 4F/sup 2/ memory cell (F: DRAM half pitch) for the sub-0.1 /spl mu/m era, we propose using the MISS tunnel diode, having a simple structure consisting of metal/insulator/p-type Si/n-type Si. We have demonstrated its feasibility for the first time by extensively studying its transport properties.