Y. Goto, K. Imai, E. Hasegawa, T. Ohashi, N. Kimizuka, T. Toda, N. Hamanaka, T. Horiuchi
{"title":"采用氟植入的三栅氧化物CMOS技术用于片上系统","authors":"Y. Goto, K. Imai, E. Hasegawa, T. Ohashi, N. Kimizuka, T. Toda, N. Hamanaka, T. Horiuchi","doi":"10.1109/VLSIT.2000.852804","DOIUrl":null,"url":null,"abstract":"We have developed a triple gate oxide CMOS technology that integrates 0.10-/spl mu/m gate length 1.2-V high-speed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and successfully reduced the gate leakage current by 1.5 orders of magnitude.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"348 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip\",\"authors\":\"Y. Goto, K. Imai, E. Hasegawa, T. Ohashi, N. Kimizuka, T. Toda, N. Hamanaka, T. Horiuchi\",\"doi\":\"10.1109/VLSIT.2000.852804\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed a triple gate oxide CMOS technology that integrates 0.10-/spl mu/m gate length 1.2-V high-speed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and successfully reduced the gate leakage current by 1.5 orders of magnitude.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"348 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852804\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852804","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip
We have developed a triple gate oxide CMOS technology that integrates 0.10-/spl mu/m gate length 1.2-V high-speed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and successfully reduced the gate leakage current by 1.5 orders of magnitude.