C. H. Diaz, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, C. Hu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, C. Wang, C.C. Wang, J. Shih, H. Hsieh, H. Tao, S. Jang, M. Yu, S. Shue, B. Chen, T. Chang, C. Hou, B. Liew, K.H. Lee, Y.C. Sun
{"title":"A 0.15 /spl mu/m CMOS foundry technology with 0.1 /spl mu/m devices for high performance applications","authors":"C. H. Diaz, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, C. Hu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, C. Wang, C.C. Wang, J. Shih, H. Hsieh, H. Tao, S. Jang, M. Yu, S. Shue, B. Chen, T. Chang, C. Hou, B. Liew, K.H. Lee, Y.C. Sun","doi":"10.1109/VLSIT.2000.852803","DOIUrl":null,"url":null,"abstract":"This paper describes a leading-edge 0.15 /spl mu/m CMOS logic foundry technology family. Advanced core devices using 20 /spl Aring/ oxides for 1.2-1.5 V operation (L/sub G min/=0.1 /spl mu/m) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 /spl Aring/ oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 /spl Aring/ gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 /spl mu/m for M1 and 0.48 /spl mu/m for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 /spl mu/m/sup 2/ demonstrated in a 2Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852803","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper describes a leading-edge 0.15 /spl mu/m CMOS logic foundry technology family. Advanced core devices using 20 /spl Aring/ oxides for 1.2-1.5 V operation (L/sub G min/=0.1 /spl mu/m) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 /spl Aring/ oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 /spl Aring/ gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 /spl mu/m for M1 and 0.48 /spl mu/m for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 /spl mu/m/sup 2/ demonstrated in a 2Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.