A 0.15 /spl mu/m CMOS foundry technology with 0.1 /spl mu/m devices for high performance applications

C. H. Diaz, M. Chang, W. Chen, M. Chiang, H. Su, S. Chang, P. Lu, C. Hu, K. Pan, C. Yang, L. Chen, C. Su, C. Wu, C. Wang, C.C. Wang, J. Shih, H. Hsieh, H. Tao, S. Jang, M. Yu, S. Shue, B. Chen, T. Chang, C. Hou, B. Liew, K.H. Lee, Y.C. Sun
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引用次数: 6

Abstract

This paper describes a leading-edge 0.15 /spl mu/m CMOS logic foundry technology family. Advanced core devices using 20 /spl Aring/ oxides for 1.2-1.5 V operation (L/sub G min/=0.1 /spl mu/m) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 /spl Aring/ oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 /spl Aring/ gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 /spl mu/m for M1 and 0.48 /spl mu/m for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 /spl mu/m/sup 2/ demonstrated in a 2Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.
一种0.15 /spl μ m CMOS代工技术,具有0.1 /spl μ m器件,适用于高性能应用
本文介绍了一个领先的0.15 /spl mu/m CMOS逻辑代工技术家族。先进的核心设备使用20 /spl /氧化物为1.2-1.5 V操作(L/sub G min/=0.1 /spl mu/m),支持高性能CPU和图形应用。该技术还支持低待机功率应用,电压为1.5 V,电压为26 /spl。外围电路的2.5或3.3 V兼容性分别使用双50或65 /spl的Aring/ gate氧化物。低k AlCu (FSG)用于七级金属互连系统,其间距非常紧密(M1级为0.39 /spl mu/m,中间级为0.48 /spl mu/m)。积极的设计规则和无边界触点/通孔使嵌入式(同步缓存)6T SRAM单元达到3.42 /spl mu/m/sup 2/,在2Mb车辆中得到了非常高的产量。整个过程的可靠性也符合标准的行业要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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