A 0.17 /spl mu/m embedded DRAM technology with 0.23 /spl mu/m/sup 2/ cell size and advanced CMOS logic

Abstract

A new 0.17 /spl mu/m embedded DRAM (eDRAM) technology is presented. Basing on a DRAM process with a cell size of 0.23 /spl mu/m/sup 2/ CMOS logic has been improved by introducing a new isolation concept called deep trench isolation and an aggressive device scaling. This is completed by a 6-level AlCu RIE metalization. This concept enables a system-on-a-chip (SOC) solution up to several hundred Mbits DRAM capacity on smallest chip size and highest yield perspectives.